ATmega8A Atmel Corporation, ATmega8A Datasheet - Page 71

• Manufacturer Part Number: ATmega8A
• Manufacturer: Atmel Corporation

Specifications of ATmega8A

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.3
14.4
14.5
8159D–AVR–02/11
Timer/Counter Clock Sources
Counter Unit
Operation
defines in a program, the precise form must be used i.e. TCNT0 for accessing Timer/Counter0
counter value and so on.
The definitions in
Table 14-1.
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located
in the Timer/Counter Control Register (TCCR0). For details on clock sources and prescaler, see
“Timer/Counter0 and Timer/Counter1 Prescalers” on page
The main part of the 8-bit Timer/Counter is the programmable counter unit.
block diagram of the counter and its surroundings.
Figure 14-2. Counter Unit Block Diagram
Signal description (internal signals):
The counter is incremented at each timer clock (clk
or internal clock source, selected by the clock select bits (CS02:0). When no clock source is
selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the
CPU, regardless of whether clk
counter clear or count operations.
The counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (MAX = 0xFF) and then restarts
from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set
in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves
like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow
BOTTOM
MAX
count
clk
max
Tn
DATA BUS
TCNTn
Definitions
The counter reaches the BOTTOM when it becomes 0x00
The counter reaches its MAXimum when it becomes 0xFF (decimal 255)
Table 14-1
are also used extensively throughout this datasheet.
count
Increment TCNT0 by 1.
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
T0
is present or not. A CPU write overrides (has priority over) all
Control Logic
max
TOVn
(Int. Req.)
clk
T0
Tn
). clk
T0
75.
can be generated from an external
Clock Select
( From Prescaler )
Detector
Edge
T0
in the following.
ATmega8A
Figure 14-2
Tn
shows a
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