ATtiny167 Automotive Atmel Corporation, ATtiny167 Automotive Datasheet - Page 184

• Manufacturer Part Number: ATtiny167 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny167 Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6.5
184
ATtiny87/ATtiny167
LIN Bit Timing Register - LINBTR
• Bit 6 - LTOERR: Frame_Time_Out Error Flag
• Bit 5 - LOVERR: Overrun Error Flag
• Bit 4 - LFERR: Framing Error Flag
• Bit 3 - LSERR: Synchronization Error Flag
• Bit 2 - LPERR: Parity Error Flag
• Bit 1 - LCERR: Checksum Error Flag
• Bit 0 - LBERR: Bit Error Flag
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
Initial Value
Read/Write
Bit
– 0 = No error,
– 1 = Frame_Time_Out error.
– 0 = No error,
– 1 = Overrun error.
– 0 = No error,
– 1 = Framing error.
– 0 = No error,
– 1 = Synchronization error.
– 0 = No error,
– 1 = Parity error.
– 0 = No error,
– 1 = Checksum error.
– 0 = no error,
– 1 = Bit error.
– 0 = Bit timing re-synchronization enabled (default),
– 1 = Bit timing re-synchronization disabled.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
LDISR
R/W
7
0
R
6
0
-
LBT5
R/(W)
5
1
R/(W)
LBT4
4
0
R/(W)
LBT3
3
0
LBT2
R/(W)
2
0
LBT1
R/(W)
1
0
R/(W)
LBT0
0
0
7728G–AVR–06/10
LINBTR