ATtiny84 Atmel Corporation, ATtiny84 Datasheet - Page 115

• Manufacturer Part Number: ATtiny84
• Manufacturer: Atmel Corporation

Specifications of ATtiny84

• Flash (kbytes): 8 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 6
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13. Timer/Counter Prescaler
13.1
13.2
8006K–AVR–10/10
Prescaler Reset
External Clock Source
Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counters. Tn
is used as a general name, n = 0, 1.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/CounterCounter, and it is shared by the Timer/Counter Tn. Since the prescaler is not
affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for
situations where a prescaled clock is used. One example of prescaling artifacts occurs when the
timer is enabled and clocked by the prescaler (CSn2:0 = 2, 3, 4, or 5). The number of system
clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 sys-
tem clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
The Prescaler Reset can be used for synchronizing the Timer/Counter to program execution.
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
equivalent block diagram of the Tn synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
high period of the internal system clock.
Figure 13-1. T0 Pin Sampling
The edge detector generates one clk
= 6) edge it detects. The synchronization and edge detector logic introduces a delay of 2.5 to 3.5
system clock cycles from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
CLK_I/O
Tn
clk
I/O
/1024.
D
LE
CLK_I/O
Q
ExtClk
Synchronization
). Alternatively, one of four taps from the prescaler can be used as a
D
< f
clk_I/O
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
T
0
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
clk
CLK_I/O
I/O
D
). The latch is transparent in the
Figure 13-1
Q
/8, f
ATtiny24/44/84
CLK_I/O
Edge Detector
/64, f
shows a functional
CLK_I/O
Tn_sync
(To Clock
Select Logic)
Tn
/256, or
). The
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