ATtiny88 Automotive Atmel Corporation, ATtiny88 Automotive Datasheet - Page 140
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATtiny88 Automotive
Manufacturer Part Number
ATtiny88 Automotive
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny88 Automotive
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Prescaling and Conversion Timing
Atmel ATtiny24/44/84 [Preliminary]
Figure 18-2. ADC Auto Trigger Logic
Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as
soon as the ongoing conversion has finished. The ADC then operates in free running mode,
constantly sampling and updating the ADC data register. The first conversion must be started
by writing a logical one to the ADSC bit in ADCSRA. In this mode, the ADC will perform suc-
cessive conversions independently of whether the ADC interrupt flag (ADIF) is cleared or not.
If auto triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
logical one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit
will be read as logical one during a conversion independently of how the conversion was
started.
Figure 18-3. ADC Prescaler
By default, the successive approximation circuitry requires an input clock frequency between
50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.The
ADC module contains a prescaler, which generates an acceptable ADC clock frequency from
any CPU frequency above 100kHz.
ADSC
SOURCE n
ADIF
SOURCE 1
.
.
.
.
ADEN
START
ADTS[2:0]
ADPS0
ADPS1
ADPS2
CK
DETECTOR
EDGE
Reset
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
START
CONVERSION
PRESCALER
LOGIC
7701E–AVR–02/11
CLK
ADC
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