ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 102
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
9.2.14.4
9.2.14.5
32002F–03/2010
Debug Communication Emulator Register (DCEMU)
Debug Communication Status Register (DCSR)
Communication Status Register. The emulator should poll the status register and read DCCPU if
the dirty bit is set.
Table 9-7.
When the emulator writes to this register, a dirty bit is set in the Debug Communication Status
register. The CPU can poll this bit to see if DCEMU contains unread data..
Table 9-8.
To avoid overruns the CPU must poll this register before writing a new value to DCCPU. Note
that the bits in this register are not automatically cleared in OCD mode. This allows a debugger
to update views and observe the system without accidentally modifying the DCSR register.
The OCD system can produce interrupts when the DCEMU register has been updated and when
the DCCPU register is read. The CPURI and EMUDI flags are set on the interrupt events, but
are cleared by software by writing the DCSR register. To enable the interrupts the corresponding
bits in the DCCR register has to be set and the Interrpt controller has to be programmed.
Table 9-9.
R/W
R/W
R/W
R/W
R/W
R
R/W
Bit Number
31:0
Bit Number
31:0
Bit Number
31:4
1
Debug Communication CPU Register
Debug Communication Emulator Register
Debug Communication Status Register
Field Name
DATA
Field Name
DATA
Field Name
Reserved
EMUDI
Init. Val.
0x0000_
0000
Init. Val.
0x0000_
0000
Init. Val.
0x0000_
0000
0
Description
Data Value
Data written by CPU
Description
Data Value
Data written by Emulator
Description
Reserved
These bits are reserved, and will always read as 0
Emulator Data Dirty Interrupt flag
0 = DCEMU has not been written to since the
clearing of this bit.
1 = DCEMU contains a new data value.
This bit is cleared by writing this bit to 0.
AVR32
102