ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet
ATxmega16D4
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ATxmega16D4 Summary of contents
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... Board control Networking • • White Goods Optical ® ® ® AVR XMEGA Microcontroller 2 C and SMBus compatible) • Hand-held battery applications • Power tools • HVAC • Metering • Medical Applications 8/16-bit XMEGA D4 Microcontroller ATxmega128D4 ATxmega64D4 ATxmega32D4 ATxmega16D4 8135J–AVR–12/10 ...
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... ATxmega16D4- ATxmega32D4- ATxmega16D4- Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green ...
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Pinout/Block Diagram Figure 2-1. Bock Diagram and TQFP/QFN pinout INDEX CORNER PA5 1 PA6 2 PA7 3 PB0 4 PB1 5 PB2 6 PB3 7 GND 8 VCC 9 PC0 10 PC1 11 Notes: 1. For full details on ...
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Figure 2-2. VFBGA pinout Top view Table 2-1. VFBGA pinout 1 A PA3 B PA4 C PA5 D PB1 E GND F VCC G PC1 8135J–AVR–12/ ...
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Overview The Atmel CMOS 8/16-bit microcontrollers based on the AVR powerful instructions in a single clock cycle, the XMEGA D4 achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption ...
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Block Diagram Figure 3-1. XMEGA D4 Block Diagram A[0..7] PORT A (8) ACA ADCA AREFA VCC/10 Int. Refs. Tempref AREFB B[0..7] PORT B (8) IRCOM 8135J–AVR–12/10 PR[0..1] XTAL1/ TOSC1 XTAL2/ TOSC2 Oscillator Circuits/ Clock PORT R (2) Generation DATA ...
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Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • XMEGA D Manual • XMEGA Application Notes This device datasheet only contains part specific information and a short ...
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AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 138 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack Pointer accessible in I/O memory space • Direct ...
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This concept enables instructions to be executed in every clock cycle. The program memory is In-System Re-programmable Flash memory. 6.3 Register File The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access ...
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Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section ...
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In-System Programmable Flash Program Memory The XMEGA D4 devices contain On-chip In-System Programmable Flash memory for program storage, see Flash address location is 16 bits. The Program Flash memory space is divided into Application and Boot sections. Both sections ...
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... To simplify development, the memory map for all Byte Address ATxmega32D4 0 I/O Registers (4KB) FFF 1000 EEPROM (1 KB) 13FF RESERVED 2000 Internal SRAM (4 KB) 2FFF 50. XMEGA D4 Byte Address ATxmega16D4 0 I/O Registers (4KB) FFF 1000 EEPROM (1 KB) 13FF RESERVED 2000 Internal SRAM (2 KB) 27FF Byte Address ATxmega128D4 0 I/O Registers (4 KB) ...
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... XMEGA A4 devices is shown in the production LOT number, wafer number, and wafer coordinates for the device. The production signature row can not be written or erased, but it can be read from both applica- tion software and external programming. Table 7-1. ATxmega16D4 ATxmega32D4 ATxmega64D4 ATxmega128D4 7.6 User Signature Row The User Signature Row is a separate memory section that is fully accessible (read and write) from application software and external programming ...
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... EEPROM is done one byte at the time. For EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 7-3. Devices EEPROM Size ATxmega16D4 1 KB ATxmega32D4 1 KB ATxmega64D4 2 KB ATxmega128D4 2 KB 8135J– ...
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Event System 8.1 Features • Inter-peripheral communication and signalling with minimum latency • CPU independent operation • 4 Event Channels allow for signals to be routed at the same time • 100% predictable timing between peripherals ...
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Figure 8-1. The Event Routing Network can directly connect together ADCs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communica- tion Module (IRCOM). Events can also be generated from software (CPU). All events ...
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System Clock and Clock options 9.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator ...
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Figure 9-1. Run-Time Calibrated Each clock source is briefly described in the following sub-sections. 9.3 Clock Options 9.3.1 32 kHz Ultra Low Power Internal Oscillator The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption ...
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Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 9.3.4 0.4 ...
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Power Management and Sleep Modes 10.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction registers to disable clocks to unused peripherals 10.2 Overview XMEGA provides various sleep modes ...
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Standby Mode Standby mode is identical to Power-down with the exception that all enabled system clock sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces the wake-up time when external crystals or resonators ...
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System Control and Reset 11.1 Features • Multiple reset sources for safe operation and device reset – Power-On Reset – External Reset – Watchdog Reset – Brown-Out Reset – PDI reset – Software reset • Asynchronous reset – No ...
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PDI reset The MCU can be reset through the Program and Debug Interface (PDI). 11.3.6 Software reset The MCU can be reset by the CPU writing to a special I/O register through a timed sequence. 12. WDT - Watchdog ...
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PMIC - Programmable Multi-level Interrupt Controller 13.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts ...
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Table 13-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x05A TWIE_INT_base 0x05E TCE0_INT_base 0x080 PORTD_INT_base 0x084 PORTA_INT_base 0x088 ACA_INT_base 0x08E ADCA_INT_base 0x09A TCD0_INT_base 0x0AE SPID_INT_vector 0x0B0 USARTD0_INT_base 8135J–AVR–12/10 Interrupt Description Two-Wire Interface on Port E Interrupt base ...
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I/O Ports 14.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events – Sense both edges – ...
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Push-pull Figure 14-1. I/O configuration - Totem-pole 14.3.2 Pull-down Figure 14-2. I/O configuration - Totem-pole with pull-down (on input) 14.3.3 Pull-up Figure 14-3. I/O configuration - Totem-pole with pull-up (on input) 14.3.4 Bus-keeper The bus-keeper’s weak output produces the ...
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Figure 14-4. I/O configuration - Totem-pole with bus-keeper 14.3.5 Others Figure 14-5. Output configuration - Wired-OR with optional pull-down Figure 14-6. I/O configuration - Wired-AND with optional pull-up 8135J–AVR–12/10 DIRn OUTn INn OUTn INn INn OUTn XMEGA ...
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Input sensing • Sense both edges • Sense rising edges • Sense falling edges • Sense low level Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure ...
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T/C - 16-bit Timer/Counter 15.1 Features • Four 16-bit Timer/Counters – Three Timer/Counters of type 0 – One Timer/Counters of type 1 • Three Compare or Capture (CC) Channels in Timer/Counter 0 • Two Compare or Capture (CC) Channels ...
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Figure 15-1. Overview of a Timer/Counter and closely related peripherals Timer/Counter Base Counter Timer Period Compare/Capture Channel B Compare/Capture Channel A Comparator The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is ...
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AWEX - Advanced Waveform Extension 16.1 Features • Output with complementary output from each Capture channel • Four Dead Time Insertion (DTI) Units, one for each Capture channel • 8-bit DTI Resolution • Separate High and Low Side Dead-Time ...
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Hi-Res - High Resolution Extension 17.1 Features • Increases Waveform Generator resolution by 2-bits (4x) • Supports Frequency, single- and dual-slope PWM operation • Supports the AWEX when this is enabled and used for the same Timer/Counter 17.2 Overview ...
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RTC - 16-bit Real-Time Counter 18.1 Features • 16-bit Timer • Flexible Tick resolution ranging from 32.768 kHz • One Compare register • One Period register • Clear timer on Overflow or Compare Match • Overflow ...
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TWI - Two-Wire Interface 19.1 Features • Two identical TWI peripherals • Simple yet Powerful and Flexible Communication Interface • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows ...
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SPI - Serial Peripheral Interface 20.1 Features • Two Identical SPI peripherals • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of ...
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USART 21.1 Features • Two Identical USART peripherals • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High-resolution Arithmetic Baud Rate Generator • Supports Serial ...
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IRCOM - IR Communication Module 22.1 Features • Pulse modulation/demodulation for infrared communication • Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed ...
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ADC - 12-bit Analog to Digital Converter 23.1 Features • One ADC with 12-bit resolution • 200 ksps sample rate • Signed and Unsigned conversions • 12 single ended inputs • 8x4 differential inputs • 3 internal inputs: – ...
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Figure 23-1. ADC overview The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop- agation delay) from 0.5 µs for 12-bit to 3.7 µs for 8-bit result. ADC conversion results are provided left- or ...
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AC - Analog Comparator 24.1 Features • Two Analog Comparators • Selectable hysteresis – No, Small or Large • Analog Comparator output available on pin • Flexible Input Selection – All pins on the port – Bandgap reference voltage. ...
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Figure 24-1. Analog comparator overview Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled 8135J–AVR–12/10 XMEGA D4 + Pin 0 output AC0 - Interrupt sensitivity control + AC1 - ...
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Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 24-1 on page ...
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OCD - On-chip Debug 25.1 Features • Complete Program Flow Control – Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor • Debugging on C and high-level language source code level • Debugging on Assembler and disassembler level ...
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Program and Debug Interface PDI - 26.1 Features • PDI - Program and Debug Interface (Atmel proprietary 2-pin interface) • Access to the OCD system • Programming of Flash, EEPROM, Fuses and Lock Bits 26.2 Overview The programming and ...
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Pinout and Pin Functions The pinout of XMEGA D4 is shown in I/O functionality, each pin may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate ...
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Communication functions SCL SDA XCKn RXDn TXDn SS MOSI MISO SCK 27.1.6 Oscillators, Clock and Event TOSCn XTALn 27.1.7 Debug/System functions RESET PDI_CLK PDI_DATA 8135J–AVR–12/10 Serial Clock for TWI Serial Data for TWI Transfer Clock for USART n Receiver ...
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Alternate Pin Functions The tables below shows the main and alternate pin functions for all pins on each port. It also shows which peripheral which make use of or enable the alternate pin function. Table 27-1. Port A - ...
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Table 27-4. Port D - Alternate functions PORTD PIN # INTERRUPT GND 18 VCC 19 PD0 20 SYNC PD1 21 SYNC PD2 22 SYNC/ASYNC PD3 23 SYNC PD4 24 SYNC PD5 25 SYNC PD6 26 SYNC PD7 27 SYNC Table ...
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Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA D4. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Table 28-1. Base Address ...
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Instruction Set Summary Mnemonics Operands Description ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry ADIW Rd, K Add Immediate to Word SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr ...
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Mnemonics Operands Description RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b ...
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Mnemonics Operands Description LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ Load Indirect and Post-Increment LD Rd, -Z Load Indirect and Pre-Decrement LDD Rd, Z+q Load ...
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Mnemonics Operands Description ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear SBI A, b Set Bit in I/O Register ...
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Packaging information 30.1 44A PIN 1 IDENTIFIER e C 0°~7° Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions ...
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D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com 8135J–AVR–12/10 E Pin #1 Corner Pin #1 Option A 1 ...
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A1 BALL BALL CORNER b Package Drawing Contact: packagedrawings@atmel.com 8135J–AVR–12/ TOP VIEW 0.35 ± 0.05 ...
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Electrical Characteristics All typical values are measured 25°C unless other temperature condition is given. All min- imum and maximum values are valid across operating temperature and voltage unless other conditions are given. 31.1 Absolute Maximum Ratings* ...
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Table 31-1. Current Consumption (Continued) Symbol Parameter Power-save mode I CC Reset Current Consumption (2) Module current consumption RC32M RC32M w/DFLL RC2M RC2M w/DFLL RC32K PLL Watchdog normal mode BOD Continuous mode BOD Sampled mode I Internal 1.00 V ref ...
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Speed Table 31-2. Symbol Clk The maximum CPU clock frequency of the XMEGA D4 devices is depending Figure 31-1 on page 60 Figure 31-1. Operating Frequency vs.Vcc 8135J–AVR–12/10 Operating voltage and frequency Parameter ...
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Flash and EEPROM Memory Characteristics Table 31-3. Endurance and Data Retention Symbol Parameter Flash EEPROM Table 31-4. Programming time Symbol Parameter Chip Erase Flash EEPROM Notes: 1. Programming is timed from the internal 2 MHz oscillator. 2. EEPROM is ...
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ADC Characteristics Table 31-5. ADC Characteristics Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Gain Error Offset Error ADC ADC Clock frequency clk Conversion rate Conversion time (propagation delay) Sampling Time Conversion range AVCC Analog Supply Voltage ...
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Analog Comparator Characteristics Table 31-7. Analog Comparator Characteristics Symbol Parameter V Input Offset Voltage off I Input Leakage Current lk V Hysteresis, No hys1 V Hysteresis, Small hys2 V Hysteresis, Large hys3 t Propagation delay delay 31.7 Bandgap Characteristics ...
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PAD Characteristics Table 31-10. PAD Characteristics Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Output Low Voltage GPIO OL V Output High Voltage GPIO OH I Input Leakage Current I/O pin IL I Input ...
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Oscillator Characteristics Table 31-13. Internal 32.768 kHz Oscillator Characteristics Symbol Parameter Accuracy Table 31-14. Internal 2 MHz Oscillator Characteristics Symbol Parameter Accuracy DFLL Calibration step size Table 31-15. Internal 32 MHz Oscillator Characteristics Symbol Parameter Accuracy DFLL Calibration stepsize ...
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Figure 31-2. TOSC input capacitance The input capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without external capacitors. Table 31-18. Device wake-up time from sleep Symbol Parameter Idle Sleep, Standby ...
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Typical Characteristics 32.1 Active Supply Current Figure 32-1. Figure 32-2. 8135J–AVR–12/10 Active Supply Current vs. Frequency 1.0 MHz External clock 25°C. SYS 700 600 500 400 300 200 100 0 0 0.1 0.2 ...
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Figure 32-3. Figure 32-4. 8135J–AVR–12/10 Active Supply Current vs. Vcc f = 1.0 MHz External Clock. SYS 800 700 600 500 400 300 200 100 0 1.6 1.8 2 2.2 2.4 Active Supply Current vs. VCC f = 32.768 kHz ...
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Figure 32-5. Figure 32-6. Active Supply Current vs. Vcc 8135J–AVR–12/10 Active Supply Current vs. Vcc f = 2.0 MHz internal RC. SYS 1600 1400 1200 1000 800 600 400 200 0 1.6 1.8 2 2.2 2 MHz ...
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Figure 32-7. 32.2 Idle Supply Current Figure 32-8. 8135J–AVR–12/10 Active Supply Current vs. Vcc MHz internal RC. SYS 2.7 2.8 2.9 3 3.1 Idle Supply Current vs. Frequency ...
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Figure 32-9. Figure 32-10. Idle Supply Current vs. Vcc 8135J–AVR–12/10 Idle Supply Current vs. Frequency MHz 25°C. SYS 1 Frequency [MHz] ...
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Figure 32-11. Idle Supply Current vs. Vcc Figure 32-12. : Idle Supply Current vs. Vcc 8135J–AVR–12/ 32.768 kHz internal RC. SYS 1.6 1.8 2 2.2 2 2.0 ...
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Figure 32-13. Idle Supply Current vs. Vcc Figure 32-14. : Idle Supply Current vs. Vcc 8135J–AVR–12/ MHz internal RC prescaled to 8 MHz. SYS 3000 2500 2000 1500 1000 500 0 1.6 1.8 2 2.2 2.4 f ...
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Power-down Supply Current Figure 32-15. Power-down Supply Current vs. Temperature Figure 32-16. Power-down Supply Current vs. Temperature 8135J–AVR–12/10 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -40 -30 -20 - Temperature [°C] With WDT and ...
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Power-save Supply Current Figure 32-17. Power-save Supply Current vs. Temperature 32.5 Pin Pull-up Figure 32-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage 8135J–AVR–12/10 With WDT, sampled BOD and RTC from ULP enabled. 3 2.5 2 1.5 1 0.5 ...
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Figure 32-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage Figure 32-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage 8135J–AVR–12/ 3.0V. CC 160 140 120 100 0 3.3V. ...
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Pin Output Voltage vs. Sink/Source Current Figure 32-21. I/O Pin Output Voltage vs. Source Current Figure 32-22. I/O Pin Output Voltage vs. Source Current 8135J–AVR–12/10 Vcc = 1.8V. 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ...
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Figure 32-23. I/O Pin Output Voltage vs. Source Current Figure 32-24. I/O Pin Output Voltage vs. Sink Current 8135J–AVR–12/10 Vcc = 3.3V. 3.5 3 2.5 2 1.5 1 0 Vcc = 1.8V. 1.8 1.6 ...
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Figure 32-25. I/O Pin Output Voltage vs. Sink Current Figure 32-26. I/O Pin Output Voltage vs. Sink Current 8135J–AVR–12/10 Vcc = 3.0V. 0.7 0.6 0.5 0.4 0.3 0.2 0 Vcc = 3.3V. 0.7 0.6 ...
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Pin Thresholds and Hysteresis Figure 32-27. I/O Pin Input Threshold Voltage vs. V Figure 32-28. I/O Pin Input Threshold Voltage vs. V 8135J–AVR–12/ I/O Pin Read as “1”. IH 2.5 2 1.5 1 0.5 0 1.6 1.8 ...
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Figure 32-29. I/O Pin Input Hysteresis vs. V Figure 32-30. Reset Input Threshold Voltage vs. V 8135J–AVR–12/10 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2 2.2 2 I/O Pin Read as “1”. IH 1.8 1.6 ...
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Figure 32-31. Reset Input Threshold Voltage vs. V 32.8 Bod Thresholds Figure 32-32. BOD Thresholds vs. Temperature 8135J–AVR–12/ I/O Pin Read as “0”. IL 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 ...
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Figure 32-33. BOD Thresholds vs. Temperature 32.9 Analog Comparator Figure 32-34. Analog Comparator Hysteresis vs. V 8135J–AVR–12/10 BOD Level = 2.9V. 3.03 3.02 3.01 Rising Vcc 3 2.99 2.98 2.97 2.96 Falling Vcc 2.95 2.94 2.93 -40 -30 -20 -10 ...
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Figure 32-35. Analog Comparator Hysteresis vs. V Figure 32-36. Analog Comparator Propagation Delay vs. V 8135J–AVR–12/10 High-speed, Large hysteresis 1.6 1.8 2 2.2 2.4 High-speed. 180 162 144 126 108 ...
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Oscillators and Wake-up Time 32.10.1 Internal 32.768 kHz Oscillator Figure 32-37. Internal 32.768 kHz Oscillator Calibration Step Size 32.10.2 Internal 2 MHz Oscillator Figure 32-38. Internal 2 MHz Oscillator CALA Calibration Step Size -0.10 % -0.20 % -0.30 % ...
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Figure 32-39. Internal 2 MHz Oscillator CALB Calibration Step Size 32.10.3 Internal 32 MHZ Oscillator Figure 32-40. Internal 32 MHz Oscillator CALA Calibration Step Size 8135J–AVR–12/10 ° - 3V. CC 3.00 % 2.50 ...
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Figure 32-41. Internal 32 MHz Oscillator CALB Calibration Step Size 32.11 Module current consumption Figure 32-42. AC current consumption vs. Vcc 8135J–AVR–12/10 ° - 3V. CC 3.00 % 2.50 % 2.00 % 1.50 ...
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Figure 32-43. Power-up current consumption vs. Vcc 32.12 Reset Pulsewidth Figure 32-44. Minimum Reset Pulse Width vs. Vcc 8135J–AVR–12/10 600 500 400 300 200 100 0 0.4 0.6 0.8 1 100 1.6 1.8 2 2.2 ...
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PDI Speed Figure 32-45. PDI Speed vs. Vcc 8135J–AVR–12/ 1.6 1.8 2 2.2 2.4 XMEGA D4 2.6 2.8 3 3.2 3 °C 3.6 89 ...
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... Errata 33.1 ATxmega16D4, ATxmega32D4 33.1.1 rev. A/B • Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously • VCC voltage scaler for AC is non-linear • ADC gain stage cannot be used for single conversion • ADC has increased INL error for some operating conditions • ...
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Figure 33-1. Analog Comparator Voltage Scaler vs. Scalefac Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not ...
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Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2 order to get a cor- rect result, or keep ADC voltage reference below 2 ADC ...
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Problem fix/Workaround Table 33-1. PGM 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation ...
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Problem fix/Workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog ...
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Problem fix/Workaround Clear the flag in software after address interrupt. 23. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag ...
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Problem fix/Workaround Wait at least one ULP clock cycle before executing a WDR instruction. 27. TWIE is not available The TWI module on PORTE, TWIE is not available Problem fix/Workaround Use the identical TWI module on PORTC, TWIC instead. 28. ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revisions in this section are referring to the document revision. 34.1 8135J – 12/ ...
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Updated the device ...
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Added ”Electrical Characteristics” on page Added ”Typical Characteristics” on page Initial revision. XMEGA D4 58. 67. 99 ...
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Table of Contents Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 5 4 Resources ................................................................................................. 7 5 Disclaimer ................................................................................................. 7 6 AVR CPU ................................................................................................... 8 7 Memories ................................................................................................ ...
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System Control and Reset .................................................................... 22 12 WDT - Watchdog Timer ......................................................................... 23 13 PMIC - Programmable Multi-level Interrupt Controller ....................... 24 14 I/O Ports .................................................................................................. 26 15 T/C - 16-bit Timer/Counter ..................................................................... 30 16 AWEX - Advanced Waveform ...
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TWI - Two-Wire Interface ....................................................................... 35 20 SPI - Serial Peripheral Interface ............................................................ 36 21 USART ..................................................................................................... 37 22 IRCOM - IR Communication Module .................................................... 38 23 ADC - 12-bit Analog to Digital Converter ............................................. ...
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... Idle Supply Current ..........................................................................................70 32.3 Power-down Supply Current ............................................................................74 32.4 Power-save Supply Current .............................................................................75 32.5 Pin Pull-up .......................................................................................................75 32.6 Pin Output Voltage vs. Sink/Source Current ...................................................77 32.7 Pin Thresholds and Hysteresis ........................................................................80 32.8 Bod Thresholds ...............................................................................................82 32.9 Analog Comparator .........................................................................................83 32.10 Oscillators and Wake-up Time ........................................................................85 32.11 Module current consumption ...........................................................................87 32.12 Reset Pulsewidth .............................................................................................88 32.13 PDI Speed .......................................................................................................89 33.1 ATxmega16D4, ATxmega32D4 .......................................................................90 34.1 8135J – 12/10 ..................................................................................................97 8135J–AVR–12/10 ...
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34.2 8135I – 10/10 ...................................................................................................97 34.3 8135H – 09/10 .................................................................................................97 34.4 8135G – 08/10 .................................................................................................97 34.5 8135F – 02/10 .................................................................................................97 34.6 8135E – 02/10 .................................................................................................98 34.7 8135D – 12/09 .................................................................................................98 34.8 8135C – 10/09 .................................................................................................98 34.9 8135B – 09/09 .................................................................................................99 ...
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