ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 39

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21. TWI - Two Wire Interface
21.1
21.2
8386A–AVR–07/11
Features
Overview
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The Two Wire Interface is a bi-directional two-wire communication interface. It is I
Management Bus (SMBus) compatible. The only external hardware needed to implement the
bus is one pull-up resistor on each bus line.
The TWI module supports master and slave functionality. The master and slave functionality are
separated from each other and can be enabled and configured separately. The master module
supports multi-master bus operation and arbitration. It contains the baud rate generator. Both
100kHz and 400kHz bus frequency is supported.
The slave module implements 7-bit address match and general address call recognition in hard-
ware. 10-bit addressing is also supported. A dedicated address mask register can act as a
second address match register or as a register for address range masking. The slave continues
to operate in all sleep modes, including Power down mode. This enables the slave to wake up
the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead. Smart Mode can be enabled to auto trigger
operations and reduce software complexity.
The TWI module will detect START and STOP conditions, bus collision and bus errors. Arbitra-
tion lost, errors, collision and clock hold on the bus is also detected and indicated in separate
status flags available in both master and slave mode.
It is possible to disable the TWI drivers in the device, and enable a 4-wire digital interface for
connecting to an external TWI bus driver. This can be used for applications where the device
operates from a different VCC voltage than used by the TWI bus.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
Two Identical Two Wire Interface peripherals
Bi-directional two-wire communication interface
Bus master and slave operation supported
Flexible slave address match functions
Slave can operate in all sleep modes
Slave address match can wake device from all sleep modes
100kHz and 400kHz bus frequency support
Slew-rate limited output drivers
Input filter for bus noise and spike suppression
Support arbitration between START/Repeated START and Data Bit (SMBus)
Slave arbitration allows support for Address Resolve Protocol (ARP) (SMBus)
– Phillips I
– System Management Bus (SMBus) compatible
– Slave operation
– Single bus master operation
– Bus master in multi-master bus environment
– Multi-master arbitration
– 7-bit and General Call Address Recognition in Hardware
– 10-bit addressing supported
– Address mask register for dual address match or address range masking
– Optional software address recognition for unlimited number of addresses
2
C compatible
XMEGA A3U
2
C and System
39