ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 43

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ATxmega32A4

Manufacturer Part Number
ATxmega32A4
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega32A4

Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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26. DAC - 12-bit Digital to Analog Converter
26.1
26.2
8069Q–AVR–12/10
Features
Overview
The XMEGA A4 devices feature one 12-bit, 1 Msps DAC with built-in offset and gain calibration,
see
A DAC converts a digital value into an analog signal. The DAC may use an internal 1.0 voltage
as the upper limit for conversion, but it is also possible to use the supply voltage or any applied
voltage in-between. The external reference input is shared with the ADC reference input.
Figure 26-1. DAC overview
The DAC has one continuous output with high drive capabilities for both resistive and capacitive
loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H)
channels, each with separate data conversion registers.
A DAC conversion may be started from the application software by writing the data conversion
registers. The DAC can also be configured to do conversions triggered by the Event System to
have regular timing, independent of the application software. DMA may be used for transferring
data from memory locations to DAC data registers.
The DAC has a built-in calibration system to reduce offset and gain error when loading with a
calibration value from software.
PORTB has one DAC. Notation of this peripheral is DACB.
One DAC with 12-bit resolution
Up to 1 Msps conversion rate
Flexible conversion range
Multiple trigger sources
1 continuous output or 2 Sample and Hold (S/H) outputs
Built-in offset and gain calibration
High drive capabilities
Low Power Mode
Figure 26-1 on page
Channel A
Channel B
Register
Register
43.
Reference selection
Configuration
Trigger
DAC
Event
Channel A
Channel B
XMEGA A4
43

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