ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 181
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ATxmega32A4U
Manufacturer Part Number
ATxmega32A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32A4U
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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14.12.5
14.12.6
8331A–AVR–07/11
CTRLE – Control Register E
INTCTRLA – Interrupt Enable Register A
Table 14-6.
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1:0 – BYTEM[1:0]: Byte Mode
These bits select the timer/counter operation mode according to
Table 14-7.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
BYTEM[1:0]
EVSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1nnn
00
01
10
11
Timer event source selection.
7
–
R
0
Clock select.
R
7
–
0
NORMAL
BYTEMODE
SPLITMODE
Group Configuration
Group Configuration
R
6
–
0
R
6
–
0
OFF
CHn
R
5
–
0
R
5
–
0
Timer/counter is set to normal mode (timer/counter type 0)
Upper byte of the counter (CNTH) will be set to zero after
each counter clock cycle
Timer/counter 0 is split into two 8-bit timer/counters
(timer/counter type 2)
Reserved
Description
Event Source
None
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Event channel n, n={0,...,7}
R
4
–
0
R
4
–
0
Atmel AVR XMEGA AU
R/W
3
–
R
0
3
ERRINTLVL[1:0]
0
R/W
R
2
–
0
2
0
Table 14-7 on page
R/W
R
1
0
1
OVFINTLVL[1:0]
0
BYTEM[1:0]
R/W
R/W
0
0
0
0
181.
INTCTRLA
CTRLE
181
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