ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 9
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Quantity
Price
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3.7
3.8
8331A–AVR–07/11
Status Register
Stack and Stack Pointer
Figure 3-3 on page 9
cycle, an ALU operation using two register operands is executed and the result is stored back to
the destination register.
Figure 3-3.
The status register (SREG) contains information about the result of the most recently executed
arithmetic or logic instruction. This information can be used for altering program flow in order to
perform conditional operations. Note that the status register is updated after all ALU operations,
as specified in the instruction set reference. This will in many cases remove the need for using
the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored
when returning from an interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be
used for storing temporary data. The stack pointer (SP) register always points to the top of the
stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data
are pushed and popped from the stack using the PUSH and POP instructions. The stack grows
from a higher memory location to a lower memory location. This implies that pushing data onto
the stack decreases the SP, and popping data off the stack increases the SP. The SP is auto-
matically loaded after reset, and the initial value is the highest address of the internal SRAM. If
the SP is changed, it must be set to point above address 0x2000, and it must be defined before
any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack.
The return address can be two or three bytes, depending on program memory size of the device.
For devices with 128KB or less of program memory, the return address is two bytes, and hence
the stack pointer is decremented/incremented by two. For devices with more than 128KB of pro-
gram memory, the return address is three bytes, and hence the SP is decremented/incremented
by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
Register Operands Fetch
ALU Operation Execute
Total Execution Time
Result Write Back
Single Cycle ALU Operation
shows the internal timing concept for the register file. In a single clock
clk
CPU
T1
Atmel AVR XMEGA AU
T2
T3
T4
9
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