M42800A Atmel Corporation, M42800A Datasheet - Page 231
M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI 0029G
When the BYPASS instruction is loaded into the instruction register, all the scan cells
assume their normal system mode of operation. The BYPASS instruction has no effect
on the system pins:
•
•
•
All unused instruction codes default to the BYPASS instruction.
BYPASS does not enable the processor to exit debug state or synchronize to MCLK for
a system speed access while in debug state. You must use RESTART to achieve this.
In the CAPTURE-DR state, a logic 0 is captured the bypass register.
In the SHIFT-DR state, test data is shifted into the bypass register through TDI
and shifted out through TDO after a delay of one TCK cycle. The first bit to shift
out is a zero.
In the UPDATE-DR state, the bypass register is not affected.
Note
Copyright © 1994-2001. All rights reserved.
Debug in Depth
B-13
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