M55800A Atmel Corporation, M55800A Datasheet - Page 151
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
1354D–ATARM–08/02
WD: Watchdog Timer ......................................................................... 89
SF: Special Function Registers......................................................... 94
USART: Universal Synchronous/Asynchronous
Receiver/Transmitter .......................................................................... 99
PIO Output Enable Register ............................................................................... 81
PIO Output Disable Register .............................................................................. 81
PIO Output Status Register ................................................................................ 82
PIO Input Filter Enable Register ......................................................................... 83
PIO Input Filter Disable Register ........................................................................ 83
PIO Input Filter Status Register .......................................................................... 84
PIO Set Output Data Register ............................................................................ 85
PIO Clear Output Data Register ......................................................................... 85
PIO Output Data Status Register........................................................................ 86
PIO Pin Data Status Register ............................................................................. 86
PIO Interrupt Enable Register............................................................................. 87
PIO Interrupt Disable Register............................................................................ 87
PIO Interrupt Mask Register ............................................................................... 88
PIO Interrupt Status Register.............................................................................. 88
WD User Interface .............................................................................................. 90
WD Overflow Mode Register .............................................................................. 90
WD Clock Mode Register ................................................................................... 91
WD Control Register........................................................................................... 92
WD Status Register ............................................................................................ 92
WD Enabling Sequence...................................................................................... 93
Chip Identification ............................................................................................... 94
SF User Interface................................................................................................ 94
Chip ID Register ................................................................................................. 95
Chip ID Extension Register................................................................................. 96
Reset Status Register......................................................................................... 97
SF Memory Mode Register................................................................................. 98
SF Protect Mode Register .................................................................................. 98
Pin Description.................................................................................................... 99
Baud Rate Generator........................................................................................ 100
Receiver............................................................................................................ 101
Transmitter........................................................................................................ 103
Break ................................................................................................................ 104
Peripheral Data Controller ................................................................................ 105
Interrupt Generation.......................................................................................... 105
Channel Modes................................................................................................. 105
USART User Interface ...................................................................................... 107
USART Control Register................................................................................... 108
USART Mode Register ..................................................................................... 110
USART Interrupt Enable Register..................................................................... 112
AT91X40 Series
iii