M55800A Atmel Corporation, M55800A Datasheet

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... Available in a 176-lead TQFP or 176-ball BGA Package Description The AT91M55800A is a member of the Atmel AT91 16-/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high perfor- mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption ...

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... Atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many ultra low-power applications. Absolute Maximum Ratings* Operating Temperature (Industrial).......- +85 C Storage Temperature............................-60° 150°C Voltage on V Powered Input Pins DDBU with Respect to Ground: ...........................-0.3V to +3.9V Voltage on Any Other Input Pin with Respect to Ground ...

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... 176-TQFP Package ( 3.6V, DD DDCORE T A MCK = 0 Hz All inputs driven TMS TDI, TCK, NRST = and V . DDA DDPLL AT91M55800A = -40°C to 85°C, unless otherwise A Min Typ 1.8 2.7 V DDCORE V DDCORE V DDCORE V DDCORE or 5.5 -0.3 0 -0.3 0 DDBU DDBU ...

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... Power Consumption AT91M55800A 4 The values in the following tables are measured values in the operating conditions indi- cated (i.e 3.3V, V DDIO DDCORE Board. They represent the power consumption on the V erwise specified. Table 2. Power Consumption Mode Conditions Fetch in ARM mode out of internal SRAM All peripheral clocks activated ...

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... The number of gates and the device die size are provided for the user to calculate reli- ability data with another standard and/or in another environmental model. Table 7. Reliability Data Parameter Number of Logic Gates Number of Memory Gates Device Die Size AT91M55800A Estimated Lifetime (MTBF) (Year Condition ...

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... Junction Temperature AT91M55800A 6 The average chip-junction temperature HEATSINK JC Where: • = package thermal resistance, Junction-to-ambient (°C/W), provided in Table page 5. • = package thermal resistance, Junction-to-case thermal resistance (°C/W), JC provided in Table 6 on page 5. ...

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... CSIGNAL output pins given in Min and Max in this datasheet. The input delays are given as typical values. Note: 1. The user must take into account the package capacitance load contribution (C described in Table 1 on page 3. AT91M55800A ). DDIO ) for a high DDIO + C ...

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... Temperature Derating Factor Core Voltage Derating Factor AT91M55800A 8 Figure 1. Derating Curve for Different Operating Temperatures 1.3 1.2 1.1 1 0.9 0.8 -60 -40 - Operating Temperature (°C) Figure 2. Derating Curve for Different Core Supply Voltages 3 2.5 2 1.5 1 0.5 1.8 2 2.2 2.4 2.6 Core Supply Voltage (V) Typ Case Derating Factor 100 120 140 160 180 2 ...

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... IO Voltage Derating Factor 1727E–ATARM–01/04 Figure 3. Derating Curve for Different IO Supply Voltages 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 IO Supply Voltage (V) Note: The derating factor in this example is applicable only to timings related to output pins. AT91M55800A Typ Case Derating Factor ...

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... Equivalent Load Capacitance L Duty Cycle t Startup Time ST Notes: 1. With ESR (Electrical Serie Resistor) maximum equal to 200 , C 2. With ESR maximum equal to 100 , C 3. With ESR maximum equal AT91M55800A 10 Conditions Measured at the MCKO output pin Without any additional load capacitance ...

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... MCKO t CDLH 1727E–ATARM–01/04 Conditions Conditions MCKO C derating MCKO MCKO C derating MCKO t CLMCK t CHMCK 0.5 V DDIO 0.5 V DDIO t CDHL AT91M55800A Min Max 41.8 23 CPMCK CPMCK 0. 0. CPMCK CPMCK Min Max 7.5 11.7 0.053 0.083 7.7 12.1 0.059 0.092 t CPMCK Units MHz ns ns ...

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... Figure 5. NRSTBU Assertion Sequence V DDBU RTC Oscillator Output (1) MCKO External Signal NRSTBU Internal Signal Note: 1. The MCKO Signal is certified to be valid at the NRSTBU Internal Signal rising edge. AT91M55800A 12 Min ) at a minimum at V CPRTC 0V Switch Time Typ CPRTC CPPLL ...

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... Wake Up Signal 1727E–ATARM–01/04 Table 14. Wake Up Minimum Pulse Width Symbol Parameter WK Wake Up Minimum Pulse Width 1 Figure 6. Wake Up Signal Wake Up AT91M55800A Min Pulse Width Units µs 13 ...

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... Analog Characteristics ADC AT91M55800A 14 Table 15. Channel Conversion Time Relative to ADC Clock Parameter Channel Conversion Time ADC Clock Frequency Table 16. External Voltage Reference Input Symbol Parameter ADVREF Input Voltage Range V REF ADVREF Input Resistance Table 17. Analog Inputs Parameter Input Voltage Range Input Leakage Current Input Capacitance Table 18 ...

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... Output Sink Current Slew Rate Rise or Fall Startup Time Load = (in parallel) Overshoot 100 mV@ vcm Table 23. Dynamic Performance Parameter Conditions Total Harmonic Distortion AT91M55800A Min Max ADC Clock = 500 kHz ±2 ADC Clock = 800 kHz ±4 ±2 ±4 Min Max 6 Min Max 2 ...

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... AT91M55800A 16 Table 24. Transfer Characteristics Parameter Conditions Resolution V = 3.3V ±10%, DAVREF DDA Integral Non-linearity > 2. 3.3V ±10%, DAVREF DDA Differential Non-linearity > 2.4V Offset Error Gain Error Min Max Units 10 Bit 4 LSB 4 LSB 2 LSB 4 LSB 1727E–ATARM–01/04 ...

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... EBI NWAIT Hold after MCK Rising 6 1727E–ATARM–01/04 Conditions Min 8.9 NUB C derating 0.053 NUB 8.3 NLB C derating 0.053 NLB ADD C derating 0.053 ADD 8.2 NCS C derating 0.053 NCS -0.4 5.9 AT91M55800A Max Units 17 ns 0.092 ns/pF 14.8 ns 0.092 ns/pF 15.2 ns 0.092 ns/pF 15.6 ns 0.092 ns/ ...

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... Data Out Valid after NWR High 18 NWR Minimum Pulse Width EBI 19 (1) (No Wait States) EBI NWR Minimum Pulse Width 20 (1) (Wait States) Notes: 1. The derating factor is not to be applied number of standard wait states inserted. AT91M55800A 18 . Conditions NWR C derating NWR NWR C derating ...

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... NCS NRD (5) C derating NRD NRD (5) C derating NRD NRD (1) (3) C derating NRD NRD (2) (3) C derating NRD CHMCK CPMCK AT91M55800A Min Max 8.5 14.5 0.059 0.092 7.7 14.2 0.059 0.092 8.3 14.5 0.053 0.083 7.9 12.4 0.053 0.083 -2.2 6.8 5 9.6 0.053 0.092 4.7 7.4 0.059 0.092 4.5 8 0.059 0.092 4 ...

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... If this condition is not met, the action depends on the read protocol intended for use. • Early Read Protocol: Programing an additional t • Standard Read Protocol: Programming an additional t 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed. AT91M55800A 20 Conditions Min ...

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... EBI 4 EBI 3 EBI EBI 5 6 EBI /EBI 1 2 EBI 21 EBI 23 EBI 33 EBI 22 EBI 24 EBI 34 EBI 31 EBI 25 EBI EBI 7 9 EBI 19 EBI 8 EBI EBI Wait AT91M55800A EBI 4 EBI 27-30 EBI 32 EBI 26 EBI 12-15 EBI 10 EBI 20 EBI 17 EBI EBI 18 18 Wait 21 ...

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... Peripheral Signals USART Signals AT91M55800A 22 The inputs must meet the minimum pulse width and period constraints shown in Table 29 and Table 30, and represented in Figure 8. Table 29. USART Input Minimum Pulse Width Symbol Parameter US SCK/RXD Minimum Pulse Width 1 Table 30. USART Minimum Input Period Symbol ...

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... Table 31. SPI Input Minimum Pulse Width Symbol Parameter SPI SPK/MISO/MOSI/NSS Minimum Pulse Width 1 Table 32. SPI Minimum Input Period Symbol Parameter SPI SPCK Minimum Input Period 2 Figure 9. SPI Signals MOSI/NSS SPCK AT91M55800A Min Pulse Width 3(t /2) CPMCK Min Input Period 5(t /2) CPMCK SPI 1 SPI 2 SPI 1 ...

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... Timer/Counter Signals Reset Signals AT91M55800A 24 Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(t mode and 4 Waveform Total-count Detection mode. The inputs must meet the CPMCK minimum pulse width and minimum input period shown in Table 33 and Table 34, and as represented in Figure 10 ...

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... The inputs must meet the minimum pulse width shown in Table 38 and represented in Figure 13. Table 38. PIO Input Minimum Pulse Width Symbol Parameter PIO PIO Input Minimum Pulse Width 1 Figure 13. PIO Signal PIO Inputs AT91M55800A Min Pulse Width 3(t /2) CPMCK Min Input Period 5(t /2) CPMCK AIC 2 ...

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... ICE Interface Signals AT91M55800A 26 Table 39. ICE Interface Timing Specifications Symbo l Parameter ICE NTRST Minimum Pulse Width 0 ICE NTRST High Recovery to TCK 1 High ICE NTRST High Removal from 2 TCK High ICE TCK Low Half-period 3 ICE TCK High Half-period 4 ICE TCK Period 5 ICE ...

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... TDI, TMS Hold after TCK High 7 JTAG TDO Hold Time 8 JTAG TCK Low to TDO Valid 9 JTAG Device Inputs Setup Time 10 JTAG Device Inputs Hold Time 11 JTAG Device Outputs Hold Time 12 JTAG TCK to Device Outputs Valid 13 AT91M55800A Conditions Min Max Units 19.3 -0.1 2.7 10.9 3 13.8 1.5 1 3.8 TDO C 0 ns/pF ...

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... AT91M55800A 28 Figure 15. JTAG Interface Signal JTAG NTRST TCK JTAG TMS/TDI TDO JTAG 8 JTAG Device Inputs Device Outputs JTAG 12 JTAG 0 JTAG JTAG 1 2 JTAG 5 JTAG 3 4 JTAG JTAG JTAG JTAG 1727E–ATARM–01/04 ...

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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...