R40008 Atmel Corporation, R40008 Datasheet - Page 11
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R40008
Manufacturer Part Number
R40008
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.R40008.pdf
(19 pages)
4.R40008.pdf
(20 pages)
Specifications of R40008
Flash (kbytes)
0 Kbytes
Pin Count
100
Max. Operating Frequency
75 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
256
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
No
External Bus Interface
Peripherals
Peripheral Registers
1354D–ATARM–08/02
No abort is generated when reading the internal memory or by accessing the internal
peripheral, whether the address is defined or not.
When a write-protected area is accessed, the memory controller detects it and gener-
ates an abort but does not cancel the access.
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and
can be configured from eight 1M byte banks up to four 16M bytes banks. It supports
byte, half-word and word aligned accesses.
For each of these banks, the user can program:
•
•
•
•
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device in
the case of single clock cycle access.
The AT91X40 Series’ peripherals are connected to the 32-bit wide Advanced Peripheral
Bus. Peripheral registers are only word accessible – byte and half-word accesses are
not supported. If a byte or a half-word access is attempted, the memory controller auto-
matically masks the lowest address bits and generates a word access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte
address space).
The following registers are common to all peripherals:
•
•
•
•
•
Unused bits in the peripheral registers are shown as “
upward compatibility. These bits read 0.
Number of wait states
Number of data float times (wait time after the access is finished to prevent any bus
contention in case the device is too long in releasing the bus)
Data bus width (8-bit or 16-bit)
With a 16-bit wide data bus, the user can program the EBI to control one 16-bit
device (Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16-
bit memory (Byte Write Access Mode).
Control Register – write only register that triggers a command when a one is written
to the corresponding position at the appropriate address. Writing a zero has no
effect.
Mode Register – read/write register that defines the configuration of the peripheral.
Usually has a value of 0x0 after a reset.
Data Registers – read and/or write register that enables the exchange of data
between the processor and the peripheral.
Status Register – read only register that returns the status of the peripheral.
Enable/Disable/Status Registers are shadow command registers. Writing a one in
the Enable Register sets the corresponding bit in the Status Register. Writing a one
in the Disable Register resets the corresponding bit and the result can be read in the
Status Register. Writing a bit to zero has no effect. This register access method
maximizes the efficiency of bit manipulation, and enables modification of a register
with a single non-interruptible instruction, replacing the costly read-modify-write
operation.
–
AT91X40 Series
“ and must be written at 0 for
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