SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 38
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SAM3N2A
Manufacturer Part Number
SAM3N2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
9.8
9.9
9.10
9.11
9.12
38
SysTick Timer
Real-time Timer
Real Time Clock
General Purpose Backup Registers
Nested Vectored Interrupt Controller
SAM3N Summary
• 24-bit down counter
• Self-reload capability
• Flexible System timer
• Real-time Timer, allowing backup of time with different accuracies
• Low power consumption
• Full asynchronous design
• Two hundred year calendar
• Programmable Periodic Interrupt
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
• Eight 32-bit general-purpose backup registers
• Thirty Two maskable external interrupts
• Sixteen priority levels
• Processor state automatically saved on interrupt entry, and restored on
• Dynamic reprioritization of interrupts
• Priority grouping
• Support for tail-chaining and late arrival of interrupts
• Processor state automatically saved on interrupt entry and restored on interrupt exit, with no
instruction overhead
– 32-bit Free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm register capable to generate a wake-up of the system through the Shut Down
– selection of pre-empting interrupt levels and non pre-empting interrupt levels
– back-to-back interrupt processing without the overhead of state saving and
Controller
restoration between interrupts.
11011AS–ATARM–04-Oct-10