SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 39
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SAM3N2A
Manufacturer Part Number
SAM3N2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
9.13
9.14
9.15
11011AS–ATARM–04-Oct-10
Chip Identification
UART
PIO Controllers
Table 9-1.
Table 9-2.
• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
• JTAG ID: 0x05B2E03F
• Two-pin UART
• 3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79
• Each PIO Controller controls up to 32 programmable I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of four peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
I/O Lines
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
– Input change, rising edge, falling edge, low level and level interrupt
– Debouncing and Glitch filter
Generator
Version
PIOB
PIOC
PIOA
ATSAM3N4C (Rev A)
ATSAM3N2C (Rev A)
ATSAM3N1C (Rev A)
ATSAM3N4B (Rev A)
ATSAM3N2B (Rev A)
ATSAM3N1B (Rev A)
ATSAM3N4A (Rev A)
ATSAM3N2A (Rev A)
ATSAM3N1A (Rev A)
SAM3N Chip ID Register
PIO available according to pin count
Chip Name
48 pin
21
13
-
CHIPID_CIDR
0x29540960
0x29590760
0x29580560
0x29440960
0x29490760
0x29480560
0x29340960
0x29390760
0x29380560
64 pin
32
15
-
SAM3N Summary
CHIPID_EXID
100 pin
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
32
15
32
39