SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 43
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SAM3N4A
Manufacturer Part Number
SAM3N4A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N4A
Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.4.3
11011A–ATARM–04-Oct-10
Core registers
In Thread mode, the CONTROL register controls whether the processor uses the main stack or
the process stack, see
uses the main stack. The options for processor operations are:
Table 10-1.
1.
The processor core registers are:
Program Counter
Processor
mode
Thread
Handler
Low registers
High registers
Stack Pointer
Link Register
See
“CONTROL register” on page
Summary of processor mode, execution privilege level, and stack use options
Used to
execute
Applications
Exception
handlers
FAULTMASK
CONTROL
PRIMASK
BASEPRI
SP (R13)
LR (R14)
PC (R15)
“CONTROL register” on page
PSR
R10
R11
R12
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Privilege level for
software execution
Privileged or
unprivileged
Always privileged
General-purpose registers
Program status register
Exception mask registers
CONTROL register
52.
PSP
‡
(1)
52. In Handler mode, the processor always
MSP
‡
Stack used
Main stack or process
stack
Main stack
(1)
Special registers
‡
Banked version of SP
SAM3N
43
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