SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 431
SAM3N4A
Manufacturer Part Number
SAM3N4A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N4A
Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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27.5
Table 27-1.
27.6
27.6.1
27.6.2
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Pin Name
MISO
MOSI
SPCK
NPCS1-NPCS3
NPCS0/NSS
Signal Description
Product Dependencies
I/O Lines
Power Management
Signal Description
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the SPI pins to their peripheral
functions.
Table 27-2.
The SPI may be clocked through the Power Management Controller (PMC), thus the program-
mer must first configure the PMC to enable the SPI clock.
Pin Description
Master In Slave Out
Master Out Slave In
Serial Clock
Peripheral Chip Selects
Peripheral Chip Select/Slave Select
Instance
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
I/O Lines
NPCS0
NPCS1
NPCS1
NPCS1
NPCS1
NPCS2
NPCS2
NPCS2
NPCS2
NPCS3
NPCS3
NPCS3
Signal
SPCK
MISO
MOSI
Master
Input
Output
Output
Output
Output
I/O Line
PB14
PA12
PA13
PA11
PA31
PA10
PA30
PA22
PA14
PC4
PB2
PC7
PA9
PA3
PA5
Type
Slave
Output
Input
Input
Unused
Input
SAM3N
SAM3N
Peripheral
A
A
A
B
A
A
B
B
B
B
B
B
B
B
A
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431
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