SAM3S2A Atmel Corporation, SAM3S2A Datasheet - Page 870
SAM3S2A
Manufacturer Part Number
SAM3S2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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36.6.5
36.6.5.1
870
SAM3S
PWM Controller Operations
Initialization
Before enabling the channels, they must have been configured by the software application:
• Unlock User Interface by writing the WPCMD field in the PWM_WPCR Register.
• Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if
• Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
• Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx
• Selection of the counter event selection (if CALG = 1) for each channel (CES field in the
• Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx
• Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in
• Configuration of the duty-cycle for each channel (CDTY in the PWM_CDTYx register).
• Configuration of the dead-time generator for each channel (DTH and DTL in PWM_DTx) if
• Selection of the synchronous channels (SYNCx in the PWM_SCM register)
• Selection of the moment when the WRDY flag and the corresponding PDC transfer request
• Configuration of the update mode (UPDM in the PWM_SCM register)
• Configuration of the update period (UPR in the PWM_SCUP register) if needed.
• Configuration of the comparisons (PWM_CMPxV and PWM_CMPxM).
• Configuration of the event lines (PWM_ELxMR).
• Configuration of the fault inputs polarity (FPOL in PWM_FMR)
• Configuration of the fault protection (FMOD and FFIL in PWM_FMR, PWM_FPV and
• Enable of the Interrupts (writing CHIDx and FCHIDx in PWM_IER1 register, and writing
• Enable of the PWM channels (writing CHIDx in the PWM_ENA register)
required).
register)
PWM_CMRx register)
register)
PWM_CPRDx register is possible while the channel is disabled. After validation of the
channel, the user must use PWM_CPRDUPDx register to update PWM_CPRDx as
explained below.
Writing in PWM_CDTYx register is possible while the channel is disabled. After validation of
the channel, the user must use PWM_CDTYUPDx register to update PWM_CDTYx as
explained below.
enabled (DTE bit in the PWM_CMRx register). Writing in the PWM_DTx register is possible
while the channel is disabled. After validation of the channel, the user must use
PWM_DTUPDx register to update PWM_DTx
are set (PTRM and PTRCS in the PWM_SCM register)
PWM_FPE1)
WRDYE, ENDTXE, TXBUFE, UNRE, CMPMx and CMPUx in PWM_IER2 register)
6500C–ATARM–8-Feb-11
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