SAM3S2C Atmel Corporation, SAM3S2C Datasheet - Page 399
SAM3S2C
Manufacturer Part Number
SAM3S2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
39
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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23.15.3
Register Name:
Addresses:
Access Type:
• NWE_CYCLE: Total Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse
and hold steps of the NWE and NCS signals. It is defined as:
Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles
• NRD_CYCLE: Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse
and hold steps of the NRD and NCS signals. It is defined as:
Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles
6500C–ATARM–8-Feb-11
31
23
15
–
–
7
SMC Cycle Register
30
22
14
SMC_CYCLE[0..4]
0x400E0008 [0], 0x400E0018 [1], 0x400E0028 [2], 0x400E0038 [3], 0x400E0048 [4]
Read-write
–
–
6
29
21
13
–
–
5
28
20
12
–
–
4
NWE_CYCLE
NRD_CYCLE
27
19
11
–
–
3
26
18
10
–
–
2
25
17
–
9
–
1
SAM3S
NWE_CYCLE
NRD_CYCLE
24
16
8
0
399
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