SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 12

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SAM7L128

Manufacturer Part Number
SAM7L128
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM7L128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
5. Power Considerations
5.1
5.2
5.2.1
5.2.2
12
Power Supplies
Low Power Modes
AT91SAM7L128/64 Preliminary
Off (Power Down) Mode
Backup Mode
The AT91SAM7L128/64 has six types of power supply pins and integrates a voltage regulator,
allowing the device to be supplied with only one voltage. The six power supply pin types are:
No separate ground pins are provided for the different power supplies. Only GND pins are pro-
vided and should be connected as shortly as possible to the system ground plane.
The various low power modes of the AT91SAM7L128/64 are described below.
In off (power down) mode, the entire chip is shut down. Only a low level on the FWUP pin can
wake up the AT91SAM7L128/64 (by a push-button for example). Internally, except for the
FWUP pin through VDDIO1, none of the chip is supplied.
Once the internal main power switch has been activated by FWUP, the 32 kHz RC oscillator and
the Supply Controller are supplied, then the core and peripherals are reset and the
AT91SAM7L128/64 enters in active mode. Refer to the System Controller Block Diagram,
ure 9-1 on page
At first power-up, if FWUP is tied high, the device enters off mode. The PIOA and PIOB pins’
states are undefined. PIOC and NRST pins are initialized as high impedance inputs.
Once the device enters active mode, the core and the parallel input/output controller are reset.
Then, if the chip enters off mode, PIOA and PIOB pins are configured as inputs with pull-ups and
PIOC pins as high impedance inputs.
Current consumption in this mode is typically 100 nA.
In backup mode, the supply controller, the zero-power power-on reset and the 32 kHz oscillator
(software selectable internal RC or external crystal) remain running. The voltage regulator and
the core are switched off.
Prior to entering this mode, the RTC, the backup SRAM, the brownout detector, the charge
pump, the LCD voltage regulator and the LCD controller can be set on or off separately.
• VDDOUT pin. It is the output of the voltage regulator. Output voltage can be programmed
• VDDIO1 pin. It powers the voltage regulator input and all the PIOC IO lines (1.8V-3.6V).
• VDDIO2 pin. It powers the PIOA and PIOB I/O lines (1.8V-3.6V). It is also the output of the
• VDDCORE pin. It powers the logic of the device, the PLL, the 2 MHz Fast RC oscillator, the
• VDDINLCD pin. It powers the charge pump which can be used as LCD Regulator power
from 1.55V to 1.80V by steps of 100 mV.
VDDIO1 voltage must be above 2.2V to allow the chip to start-up (POR threshold).
LCD voltage regulator. The output voltage can be programmed from 2.4V to 3.4V with 16
steps.
ADC and the Flash memory. It must be connected to the VDDOUT pin with a decoupling
capacitor.
supply. Voltage ranges from 1.8V to 3.6V.
30.
6257AS–ATARM–28-Feb-08
Fig-

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