SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 19

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6. I/O Line Considerations
6.1
6.2
6.3
6.4
6.5
6257AS–ATARM–28-Feb-08
JTAG Port Pins
Test Pin
NRST Pin
NRSTB Pin
ERASE Pin
TMS, TDI and TCK are schmitt trigger inputs. TMS, TDI and TCK do not integrate a pull-up
resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The
JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be
left unconnected for normal operations.
The TST pin is used for manufacturing test or fast programming mode of the AT91SAM7L128/64
when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to
GND, so that it can be left unconnected for normal operations.
To enter fast programming mode, the TST and CLKIN pins must be tied high while FWUP is tied
low.
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components or asserted low externally to reset the
microcontroller. There is no constraint on the length of the reset pulse and the reset controller
can guarantee a minimum pulse length.
The NRST pin integrates a permanent pull-up resistor to VDDIO1 of about 100 kΩ.
The NRSTB pin is input only and enables asynchronous reset of the AT91SAM7L128/64 when
asserted low. The NRSTB pin integrates a permanent pull-up resistor of about 15 kΩ. This
allows connection of a simple push button on the NRBST pin as a system-user reset.
In all modes, this pin will reset the chip. It can be used as an external system reset source.
In harsh environments, it is recommended to add an external capacitor (10 nF) between NRSTB
and VDDIO1.
NRSTB pin must not be connected to VDDIO1. There must not be an external pull-up on
NRSTB.
The ERASE pin is used to reinitialize the Flash content and some of its NVM bits. It integrates a
permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for nor-
mal operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high
during less than 100 ms, it is not taken into account. The pin must be tied high during more than
220 ms to perform the reinitialization of the Flash.
AT91SAM7L128/64 Preliminary
19