SAM7S128 Atmel Corporation, SAM7S128 Datasheet - Page 22

• Manufacturer Part Number: SAM7S128
• Manufacturer: Atmel Corporation

Specifications of SAM7S128

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.8
8.8.1
8.8.2
22
Embedded Flash
SAM7S Series Summary
Flash Overview
Embedded Flash Controller
The Flash benefits from the integration of a power reset cell and from the brownout detector.
This prevents code corruption during power supply changes, even in the worst conditions.
When Flash is not used (read or write access), it is automatically placed into standby mode.
The Embedded Flash Controller (EFC) manages accesses performed by the masters of the sys-
tem. It enables reading the Flash and writing the write buffer. It also contains a User Interface,
mapped within the Memory Controller on the APB. The User Interface allows:
The Embedded Flash Controller also provides a dual 32-bit prefetch buffer that optimizes 16-bit
access to the Flash. This is particularly efficient when the processor is running in Thumb mode.
Two EFCs are embedded in the SAM7S512 to control each bank of 256 Kbytes. Dual plane
organization allows concurrent Read and Program. Read from one memory plane may be per-
formed even while program or erase functions are being executed in the other memory plane.
One EFC is embedded in the SAM7S256/128/64/32/321/161/16 to control the single plane
256/128/64/32/16 Kbytes.
• The Flash of the SAM7S512 is organized in two banks (dual plane) of 1024 pages of 256
• The Flash of the SAM7S256 is organized in 1024 pages (single plane) of 256 bytes. The
• The Flash of the SAM7S128 is organized in 512 pages (single plane) of 256 bytes. The
• The Flash of the SAM7S64 is organized in 512 pages (single plane) of 128 bytes. The 65,536
• The Flash of the SAM7S321/32 is organized in 256 pages (single plane) of 128 bytes. The
• The Flash of the SAM7S161/16 is organized in 256 pages (single plane) of 64 bytes. The
• The Flash of the SAM7S512/256/128 contains a 256-byte write buffer, accessible through a
• The Flash of the SAM7S64/321/32/161/16 contains a 128-byte write buffer, accessible
• programming of the access parameters of the Flash (number of wait states, timings, etc.)
• starting commands such as full erase, page erase, page program, NVM bit set, NVM bit
• getting the end status of the last command
• getting error status
• programming interrupts on the end of the last commands or on errors
bytes. The 524,288 bytes are organized in 32-bit words.
262,144 bytes are organized in 32-bit words.
131,072 bytes are organized in 32-bit words.
bytes are organized in 32-bit words.
32,768 bytes are organized in 32-bit words.
16,384 bytes are organized in 32-bit words.
32-bit interface.
through a 32-bit interface.
clear, etc.
6175JS–ATARM–28-Jul-11