SAM7S161 Atmel Corporation, SAM7S161 Datasheet - Page 722

• Manufacturer Part Number: SAM7S161
• Manufacturer: Atmel Corporation

Specifications of SAM7S161

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.19.6.2
40.19.6.3
40.19.6.4
40.19.6.5
40.19.7
40.19.7.1
40.19.7.2
722
SAM7S Series
Serial Peripheral Interface (SPI)
PWM: Update when PWM_CPRDx = 0
PWM: Counter Start Value
PWM: Constraints on Duty Cycle Value
PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
SPI: Pulse Generation on SPCK
SPI: Bad tx_ready behavior when CSAAT=1 and SCBR = 1
When Channel Period Register equals 0, the period update is not operational.
Do not write 0 in the period register.
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter
starts at 1.
None.
Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in
left aligned mode may change the polarity of the signal.
Do not set PWM_CDTYx at 0 in center aligned mode.
Do not set PWM_CDTYx at 0 or 1 in left aligned mode.
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled
by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of
the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit
in the PWM_SR stays at 1.
Do not disable a channel before completion of one period of the selected clock.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
None.
If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed
consecutively on the same slave with an IDLE state between them, the tx_ready signal does not
rise after the second data has been transferred in the shifter. This can imply for example, that
the second data is sent twice.
Do not use the combination CSAAT=1 and SCBR =1.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
– The Baudrate is odd and different from 1
– The Polarity is set to 1
– The Phase is set to 0
6175L–ATARM–28-Jul-11