SAM7S161 Atmel Corporation, SAM7S161 Datasheet - Page 733

• Manufacturer Part Number: SAM7S161
• Manufacturer: Atmel Corporation

Specifications of SAM7S161

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.20.6.6
40.20.6.7
40.20.6.8
40.20.6.9
40.20.6.10
40.20.6.11
6175L–ATARM–28-Jul-11
SPI: Baudrate Set to 1
SPI: Disable In Slave Mode
SPI: Disable Issue
SPI: Software Reset and SPIEN Bit
SPI: CSAAT = 1 and Delay
SPI: Bad Serial Clock Generation on 2nd Chip Select
When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency)
and when the BITS field of the SPI_CSR register (number of bits to be transmitted) equals an
ODD value (in this case 9,11,13 or 15), an additional pulse will be generated on output SPCK.
Everything is OK if the BITS field equals 8,10,12,14 or 16 and Baudrate = 1.
None.
The SPI disable is not possible in slave mode.
Read first the received data, then perform the software reset.
The SPI Command “SPI Disable” is not possible during a transfer, it must be performed only
after TX_EMPTY rising else there is everlasting dummy transfers occur.
None.
The SPI Command “software reset” does not reset the SPIEN config bit. Therefore rewriting an
SPI enable command does not set TX_READY, TX_EMPTY flags.
Send SPI disable command after a software reset.
If CSAAT = 1 for current access and there is no more TX request for a time greater
than DLYBCT + DLYBCS, then if an access is requested on another slave, the NPCS bus
switches from one CS to the one requested without DLYBCS. External Slaves may reach a con-
tention on SPI_MISO line for a short period.
Assert the Last Transfer Command (NPCS de-activation) for the last character of each slave.
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• Transmitting with the slowest chip select and then with the fastest one, then an additional
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR are not equal to 1
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SAM7S Series
733