SAM7S512 Atmel Corporation, SAM7S512 Datasheet
SAM7S512
Specifications of SAM7S512
Related parts for SAM7S512
SAM7S512 Summary of contents
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... In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 512 Kbytes (SAM7S512) Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane) – ...
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... VDDCORE Core Power Supply with Brown-out Detector • Fully Static Operation MHz at 1.65V and 85⋅ C Worst Case Conditions • Available in 64-lead LQFP Green or 64-pad QFN Green Package (SAM7S512/256/128/64/321/161) and 48-lead LQFP Green or 48-pad QFN Green Package (SAM7S32/16) SAM7S Series Summary 2 ® ...
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... Their aggressive price point and high level of integration pushes their scope of use far into the cost-sensitive, high-volume consumer market. 1.1 Configuration Summary of the SAM7S512, SAM7S256, SAM7S128, SAM7S64, SAM7S321, SAM7S32, SAM7S161 and SAM7S16 The SAM7S512, SAM7S256, SAM7S128, SAM7S64, SAM7S321, SAM7S32, SAM7S161 and SAM7S16 differ in memory size, peripheral set and package ...
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... Block Diagram Figure 2-1. SAM7S512/256/128/64/321/161 Block Diagram TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ IRQ0-IRQ1 PCK0-PCK2 PLLRC PLL XIN OSC XOUT RCOSC VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 ...
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Figure 2-2. SAM7S32/16 Block Diagram TDI TDO TMS TCK JTAGSEL System Controller TST FIQ IRQ0 PCK0-PCK2 PLLRC PLL XIN OSC XOUT VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ...
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Signal Description Table 3-1. Signal Description List Signal Name Function Voltage and ADC Regulator Power Supply VDDIN Input VDDOUT Voltage Regulator Output VDDFLASH Flash Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL GND Ground ...
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Table 3-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming ...
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... Package and Pinout The SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package. The SAM7S161 is available in a 64-Lead LQFP package. The SAM7S32/16 are available in a 48-lead LQFP or 48-pad QFN package. 4.1 64-lead LQFP and 64-pad QFN Package Outlines Figure 4-1 age. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet ...
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... LQFP and 64-pad QFN Pinout Table 4-1. SAM7S512/256/128/64/321/161 Pinout 1 ADVREF 17 2 GND 18 3 AD4 19 4 AD5 20 5 AD6 21 6 AD7 22 7 VDDIN 23 8 VDDOUT 24 9 PA17/PGMD5/AD0 25 10 PA18/PGMD6/AD1 26 11 PA21/PGMD9 27 12 VDDCORE 28 13 PA19/PGMD7/AD2 29 14 PA22/PGMD10 30 15 PA23/PGMD11 31 16 PA20/PGMD8/AD3 ...
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LQFP and 48-pad QFN Package Outlines Figure 4-3 age. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 4-3. Figure 4-4. 4.4 48-lead LQFP and 48-pad QFN Pinout Table 4-2. SAM7S32/16 ...
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Power Considerations 5.1 Power Supplies The SAM7S Series has six types of power supply pins and integrates a voltage regulator, allow- ing the device to be supplied with only one voltage. The six power supply pin types are: • ...
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Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 ...
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... PIO Controller A Lines • All the I/O lines PA0 to PA31on SAM7S512/256/128/64/321 (PA0 to PA20 on SAM7S32) are 5V-tolerant and all integrate a programmable pull-up resistor. • All the I/O lines PA0 to PA31 on SAM7S161 (PA0 to PA20 on SAM7S16) are not 5V-tolerant and all integrate a programmable pull-up resistor. ...
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I/O line to VDDIO. Care should be taken, in particular at reset, as all the I/O lines default to input with the pull-up resistor enabled at reset. 6.6 I/O Line Drive Levels The PIO lines PA0 to ...
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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb • Three-stage pipeline architecture – Instruction ...
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... Interrupt generation in case of forbidden operation 7.4 Peripheral DMA Controller • Handles data transfer between peripherals and memories • Eleven channels: SAM7S512/256/128/64/321/161 • Nine channels: SAM7S32/16 – Two for each USART – Two for the Debug Unit – Two for the Serial Synchronous Controller – ...
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... Memories 8.1 SAM7S512 • 512 Kbytes of Flash Memory, dual plane – 2 contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase – Full chip erase time – ...
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SAM7S64 • 64 Kbytes of Flash Memory, single plane – 512 pages of 128 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming ...
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... Figure 8-1. SAM SAM7S512/256/128/64/321/32/161/16 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256M Bytes 0xFFFF FFFF SAM7S Series Summary 20 Internal Memory Mapping ...
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... The internal ROM is not mapped by default. 8.7.3 Internal Flash • The SAM7S512 features two contiguous banks (dual plane) of 256 Kbytes of Flash. • The SAM7S256 features one bank (single plane) of 256 Kbytes of Flash. • The SAM7S128 features one bank (single plane) of 128 Kbytes of Flash. ...
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... Embedded Flash 8.8.1 Flash Overview • The Flash of the SAM7S512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words. • The Flash of the SAM7S256 is organized in 1024 pages (single plane) of 256 bytes. The 262,144 bytes are organized in 32-bit words. ...
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... SAM7S512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The SAM7S512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR register rises and the interrupt line rises if the LOCKE bit has been written the MC_FMR register ...
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... Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. Table 8-1 Table 8-1. Flash Configuration Summary Device Number of Lock Bits SAM7S512 32 SAM7S256 16 SAM7S128 8 SAM7S64 ...
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This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is ...
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Communication through the USB Device Port is limited to an 18.432 MHz crystal. ( The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). 9. System Controller The System Controller manages all vital blocks of the microcontroller: ...
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... Figure 9-1. System Controller Block Diagram (SAM7S512/256/128/64/321/161) NRST XIN XOUT PLLRC PA0-PA31 6175JS–ATARM–28-Jul-11 wdt_irq dbgu_irq pmc_irq rstc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset Timer SLCK Real-Time Timer periph_nreset SLCK Watchdog debug idle Timer proc_nreset ...
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Figure 9-2. System Controller Block Diagram (SAM7S32/16) periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset periph_nreset en BOD POR NRST RCOSC XIN OSC XOUT PLL PLLRC periph_nreset periph_nreset periph_clk[2] PA0-PA20 SAM7S Series Summary 28 Interrupt Controller MCK Debug Unit ...
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Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether power-up reset, a software reset, a user reset, a watchdog ...
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Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 kHz and 42 kHz • Main Oscillator frequency ranges between 3 and 20 ...
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Figure 9-4. 9.4 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is ...
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... Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x270B0A40 for AT91SAM7S512 Rev A – Chip ID is 0x270B0A4F for AT91SAM7S512 Rev B – Chip ID is 0x270D0940 for AT91SAM7S256 Rev A – Chip ID is 0x270B0941 for AT91SAM7S256 Rev B – ...
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Real-time Timer • 32-bit free-running counter with alarm running on prescaled SCLK • Programmable 16-bit prescaler for SLCK accuracy compensation 9.9 PIO Controller • One PIO Controller, controlling 32 I/O lines (21 for SAM7S32/16) • Fully programmable through set/clear ...
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... Peripheral Identifiers The SAM7S Series embeds a wide range of peripherals. tifiers of the SAM7S512/256/128/64/321/161. SAM7S32/16. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Manage- ment Controller. ...
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... PIO Controller A controls 32 lines (21 lines for SAM7S32/16). Each line can be assigned to one of two peripheral functions Some of them can also be multiplexed with the analog inputs of the ADC Controller. Table 10-3, “Multiplexing on PIO Controller A (SAM7S512/256/128/64/321/161),” on page 36 and Table 10-4, “Multiplexing on PIO Controller A (SAM7S32/16),” on page 37 I/O lines of the peripherals the analog inputs are multiplexed on the PIO Controller A. The two columns “ ...
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... PIO Controller A Multiplexing Table 10-3. Multiplexing on PIO Controller A (SAM7S512/256/128/64/321/161) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 DTXD PA11 NPCS0 PA12 MISO PA13 MOSI ...
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Table 10-4. Multiplexing on PIO Controller A (SAM7S32/16) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 DTXD PA11 NPCS0 PA12 ...
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... Selectable mode fault detection – Maximum frequency Master Clock 10.6 Two-wire Interface • Master Mode only (SAM7S512/256/128/64/321/32) • Master, Multi-Master and Slave Mode support (SAM7S161/16) • General Call supported in Slave Mode (SAM7S161/16) • Compatibility with • One, two or three bytes internal address registers for easy Serial Memory access • ...
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ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication 115.2 Kbps • Test Modes ...
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PWM Controller • Four channels, one 16-bit counter per channel • Common clock generator, providing thirteen different clocks – One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs • Independent ...
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Package Drawings The SAM7S series devices are available in LQFP and QFN package types. 11.1 LQFP Packages Figure 11-1. 48-and 64-lead LQFP Package Drawing 6175JS–ATARM–28-Jul-11 SAM7S Series Summary 41 ...
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Table 11-1. Symbol θ 1 θ 2 θ aaa bbb ccc ddd SAM7S Series Summary 42 48-lead LQFP Package Dimensions (in ...
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Table 11-2. Symbol θ θ θ aaa bbb ccc ddd 6175JS–ATARM–28-Jul-11 64-lead LQFP Package Dimensions (in mm) Millimeter Min Nom – – ...
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QFN Packages Figure 11-2. 48-pad QFN Package SAM7S Series Summary 44 6175JS–ATARM–28-Jul-11 ...
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Table 11-3. Symbol aaa bbb ccc 6175JS–ATARM–28-Jul-11 48-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.050 – 0.65 0.70 0.20 REF ...
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Figure 11-3. 64-pad QFN Package Drawing ll dimensions are in mm eference : JEDEC Drawing MO-220 SAM7S Series Summary 46 6175JS–ATARM–28-Jul-11 ...
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Table 11-4. Symbol aaa bbb ccc 6175JS–ATARM–28-Jul-11 64-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.05 – 0.65 0.70 0.20 REF ...
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... AT91SAM7S32-AU-001 AT91SAM7S32B-AU AT91SAM7S32-MU AT91SAM7S32B-MU AT91SAM7S321-AU AT91SAM7S321-MU AT91SAM7S64B-AU – AT91SAM7S64B-MU AT91SAM7S128-AU-001 – AT91SAM7S128-MU AT91SAM7S256-AU-001 – AT91SAM7S256-MU AT91SAM7S512-AU AT91SAM7S512B-AU AT91SAM7S512-MU AT91SAM7S512B-MU SAM7S Series Summary 48 MLR C Ordering Code – – – – – – – AT91SAM7S64C-AU AT91SAM7S64C-MU AT91SAM7S128C-AU AT91SAM7S128C-MU AT91SAM7S256C-AU AT91SAM7S256C-MU – ...
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... Section 12. ”SAM7S Ordering Information” 6175ES Section 10.11 on page 40 “Features” on page 1, and global: AT91SAM7S512 added to series. Reference to Manchester Encoder removed from USART. Section 8. ”Memories” Section 10. ”Peripherals” Section 11. ”Package Drawings” “ice_nreset” signals changed to” power_on_reset” in System Controller block diagrams, ...
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... Registers”, chip IDs updated, added SAM7S32 Rev Information”, Updated product ordering information by MRL A and MRL B Assistant”, added to SAM-BA Boot recovery procedure, a power cycle of the Table 12-1, “SAM7S Series Ordering Information”. 32, Chip ID is 0x270B0A4F for AT91SAM7S512 Rev B Change Request Ref. 5846 ...
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