SAM7S512 Atmel Corporation, SAM7S512 Datasheet - Page 16

• Manufacturer Part Number: SAM7S512
• Manufacturer: Atmel Corporation

Specifications of SAM7S512

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7. Processor and Architecture
7.1
7.2
7.3
16
ARM7TDMI Processor
Debug and Test Features
Memory Controller
SAM7S Series Summary
• RISC processor based on ARMv4T Von Neumann architecture
• Two instruction sets
• Three-stage pipeline architecture
• Integrated EmbeddedICE
• Debug Unit
• IEEE1149.1 JTAG Boundary-scan on all digital pins
• Bus Arbiter
• Address decoder provides selection signals for
• Abort Status Registers
• Misalignment Detector
• Remap Command
• Embedded Flash Controller
– Runs at up to 55 MHz, providing 0.9 MIPS/MHz
– ARM
– Thumb
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID Register
– Handles requests from the ARM7TDMI and the Peripheral DMA Controller
– Three internal 1 Mbyte memory areas
– One 256 Mbyte embedded peripheral area
– Source, Type and all parameters of the access leading to an abort are saved
– Facilitates debug by detection of bad pointers
– Alignment checking of all data accesses
– Abort generation in case of misalignment
– Remaps the SRAM in place of the embedded non-volatile memory
– Allows handling of dynamic exception vectors
– Embedded Flash interface, up to three programmable wait states
®
high-performance 32-bit instruction set
®
high code density 16-bit instruction set
™
(embedded in-circuit emulator)
6175JS–ATARM–28-Jul-11