SAM7S512 Atmel Corporation, SAM7S512 Datasheet - Page 250
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SAM7S512
Manufacturer Part Number
SAM7S512
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S512
Flash (kbytes)
512 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug in Depth
B.10
B.10.1 Breakpoint with Prefetch Abort
B.10.2 Interrupts
B.10.3 Data Aborts
B-32
Priorities and exceptions
When a breakpoint, or a debug request occurs, the normal flow of the program is
interrupted. Debug can be treated as another type of exception. The interaction of the
debugger with other exceptions is described in Behavior of the program counter during
debug on page B-29. This section covers the following priorities:
•
•
•
When a breakpointed instruction fetch causes a Prefetch Abort, the abort is taken and
the breakpoint is disregarded. Usually, Prefetch Aborts occur when, for example, an
access is made to a virtual address that does not physically exist and the returned data
is therefore invalid. In such a case, the normal action of the operating system is to swap
in the page of memory and to return to the previously-invalid address. This time, when
the instruction is fetched and providing the breakpoint is activated, it can be
data-dependent, the ARM7TDMI core enters debug state.
The Prefetch Abort, therefore, takes higher priority than the breakpoint.
When the ARM7TDMI core enters debug state, interrupts are automatically disabled.
If an interrupt is pending during the instruction prior to entering debug state, the
ARM7TDMI core enters debug state in the mode of the interrupt. On entry to debug
state, the debugger cannot assume that the ARM7TDMI core is in the mode expected
by the user program. The ARM7TDMI core must check the PC, the CPSR, and the
SPSR to accurately determine the reason for the exception.
Debug, therefore, takes higher priority than the interrupt, but the ARM7TDMI core
does remember that an interrupt has occurred.
When a Data Abort occurs on a watchpointed access, the ARM7TDMI core enters
debug state in abort mode. The watchpoint, therefore, has higher priority than the abort,
but the ARM7TDMI core remembers that the abort happened.
Breakpoint with Prefetch Abort on page B-32
Interrupts on page B-32
Data Aborts on page B-32.
Copyright © 1994-2001. All rights reserved.
ARM DDI 0029G
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