SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 102
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
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- Download datasheet (2Mb)
Caches and Write Buffer
4-6
Table 4-3 gives the CP15 c1 C and M bit settings for DCache, and the associated
behavior.
Table 4-4 gives the page table C and B bit settings for the DCache (CP15 c1 C bit = M
bit = 1), and the associated behavior.
Page
table
C bit
0
0
1
CP15
c1 C bit
0
1
1
Copyright © 2001-2003 ARM Limited. All rights reserved.
Page
table
B bit
0
1
0
CP15
c1 M bit
0
0
1
Description
Noncachable,
nonbufferable
Noncachable,
bufferable
Write-through
ARM926EJ-S behavior
DCache disabled. All data accesses are to the external memory.
DCache enabled, MMU disabled. The C bit is overriden by the M bit
setting, which means that the DCache is effectively disabled. All
data accesses are noncachable, nonbufferable, with no protection
checks. All addresses are flat mapped, that is VA = MVA = PA.
DCache enabled, MMU enabled. All data accesses are cachable or
noncachable depending on the page descriptor C bit and B bit (see
Table 4-4), and protection checks are performed. All addresses are
remapped from VA to PA, depending on the MMU page table entry,
that is the VA is translated to an MVA, and the MVA is remapped to
a PA.
Table 4-4 Page table C and B bit settings for the DCache
Table 4-3 CP15 c1 C and M bit settings for the DCache
ARM926EJ-S behavior
DCache disabled. Read from external memory. Write as
a nonbuffered store(s) to external memory. DCache is not
updated.
DCache disabled. Read from external memory. Write as
a buffered store(s) to external memory. DCache is not
updated.
DCache enabled:
Read hit
Read miss
Write hit
Write miss
Read from DCache
Linefill
Write to the DCache, and buffered store
to external memory
Buffered store to external memory
ARM DDI0198D
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