SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 793
SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 793 of 903
- Download datasheet (13Mb)
41.5.22
Name:
Access Type:
• FRCESTALL: Stall Handshake Request
0 = no effect.
1= If set a STALL answer will be done to the host for the next handshake.
This bit is reset by hardware upon received SETUP.
• TOGGLESQ_STA: Toggle Sequencing
Toggle Sequencing:
Note 1: In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT
Data = 1).
Note 2:These bits are updated for OUT transfer:
Note 3: For High Bandwidth Isochronous Out endpoint, it is recommended to check the UDPHS_EPTSTAx/ERR_TRANS
bit to know if the toggle sequencing is correct or not.
Note 4: This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx
(disable endpoint).
6289D–ATARM–3-Oct-11
00
01
10
11
SHRT_PCKT
NAK_OUT
IN endpoint: it indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the cur-
rent bank.
CONTROL and OUT endpoint:
These bits are set by hardware to indicate the PID data of the current bank:
– a new data has been written into the current bank.
– the user has just cleared the Received OUT Data bit to switch to the next bank.
31
23
15
7
TOGGLESQ_STA
Data0
Data1
Data2 (only for High Bandwidth Isochronous Endpoint)
MData (only for High Bandwidth Isochronous Endpoint)
UDPHS Endpoint Status Register
ERR_FLUSH
NAK_IN/
30
22
14
Read-only
6
UDPHS_EPTSTAx [x=0..6]
BYTE_COUNT
ERR_CRISO/
ERR_NBTRA
STALL_SNT/
FRCESTALL
29
21
13
5
ERR_FL_ISO
RX_SETUP/
28
20
12
4
–
BYTE_COUNT
TX_PK_RDY/
ERR_TRANS
27
19
11
BUSY_BANK_STA
3
–
TX_COMPLT
AT91SAM9R64/RL64
26
18
10
2
–
RX_BK_RDY/
KILL_BANK
25
17
CURRENT_BANK/
9
1
–
CONTROL_DIR
ERR_OVFLW
24
16
8
0
–
793
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