SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 150
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SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 150 of 248
- Download datasheet (2Mb)
Bus Interface Unit
6.2.6
6.2.7
6-10
External Abort limitations
AHB clocking
from ARM926EJ-S
D/IHCLKEN
to ARM926EJ-S
AHB outputs
AHB inputs
HCLK
CLK
The ARM926EJ-S design uses a single clock, CLK. To run the ARM926EJ-S processor
at a higher frequency than the AHB system bus, a separate AHB clock enable for each
of the two bus masters is required (in a multi-AHB system each AHB system can be
running at a different frequency):
DHCLKEN
IHCLKEN
Figure 6-3 shows the relationships between CLK, HCLK, DHCLKEN, and
IHCLKEN.
For single and multi-layer AHB systems, DHCLKEN and IHCLKEN must be tied
together. If HCLK and CLK are the same frequency, the relevant HCLKEN input (or
inputs) must be tied HIGH.
CLK and HCLK must be synchronous. The skew between CLK and HCLK must be
minimized.
Only certain types of accesses cause an External Abort if an Error response is returned
for an AHB transfer. These are:
•
•
•
•
Copyright © 2001-2003 ARM Limited. All rights reserved.
page table walk
noncached read
nonbuffered write
noncached read-lock-write (SWP).
Is used to signify the rising edge of HCLK for the system data
BIU bus master.
Is used to signify the rising edge of HCLK for the system
instruction BIU bus master.
Figure 6-3 AHB clock relationships
Skew between CLK and HCLK
ARM DDI0198D
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