SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 236
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SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 236 of 248
- Download datasheet (2Mb)
Glossary
Index
Index register
Instruction cache
Instruction cycle count
Instruction Memory Barrier (IMB)
Internal scan chain
Interrupt handler
Interrupt vector
Invalidate
Joint Test Action Group (JTAG)
JTAG
Line
Little-endian
Glossary-12
See Cache index.
A register specified in some load or store instructions. The value of this register is used
as an offset to be added to or subtracted from the base register value to form the virtual
address, which is sent to memory. Some addressing modes optionally enable the index
register value to be shifted prior to the addition or subtraction.
A block of on-chip fast access memory locations, situated between the processor and
main memory, used for storing and retrieving copies of often used instructions. This is
done to greatly reduce the average speed of memory accesses and so to increase
processor performance.
The number of cycles for which an instruction occupies the Execute stage of the
pipeline.
An operation to ensure that the prefetch buffer is flushed of all out-of-date instructions.
A series of registers connected together to form a path through a device, used during
production testing to import test patterns into internal nodes of the device and export the
resulting values.
A program that control of the processor is passed to when an interrupt occurs.
One of a number of fixed addresses in low memory, or in high memory if high vectors
are configured, that contains the first instruction of the corresponding interrupt handler.
To mark a cache line as being not valid by clearing the valid bit. This must be done
whenever the line does not contain a valid cache entry. For example, after a cache flush
all lines are invalid.
The name of the organization that developed standard IEEE 1149.1. This standard
defines a boundary-scan architecture used for in-circuit testing of integrated circuit
devices. It is commonly known by the initials JTAG.
See Joint Test Action Group.
See Cache line.
Byte ordering scheme in which bytes of increasing significance in a data word are stored
at increasing addresses in memory.
See also Big-endian and Endianness.
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
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