SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 182
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 182 of 290
- Download datasheet (5Mb)
Instruction Cycle Times
8-22
instruction, but the second
For example, the following sequence incurs a two-cycle interlock on the first
LDRB
ADD
ADD
A two-cycle interlock refers to the number of unwaited ARM9E-S clock cycles to
which the interlock applies. If a multi-cycle instruction separates a load instruction and
the instruction using the result of the load, then no interlock can apply. The following
example does not incur an interlock:
LDRB
MUL
ADD
There is no forwarding path from loaded data to the C read port of the register bank,
which is used for the store data of
operand of multiply accumulate instructions. The result of a load must reach the Write
stage of the pipeline before it can be made available at the C read port, resulting in a
single-cycle load-use interlock from loaded data to the C read port.
The following example incurs a single-cycle interlock:
LDR
STR
The following example also incurs a single-cycle interlock:
LDR
MLA
The following example does not incur an interlock:
LDR
NOP ** Code to be changed to remove NOP **
STR
Most interlock conditions are determined when the instruction being interlocked is still
in the Decode stage of the pipeline. Load multiple and Store multiple instructions can
incur a Decode stage interlock when the base register is not available due to a previous
instruction. Store multiple instructions can also incur an Execute stage interlock when
the first register to be stored is not available due to a previous instruction. This is
referred to as a second-cycle interlock.
The following example incurs a single-cycle interlock:
LDR
STMIA
Copyright © 2000 ARM Limited. All rights reserved.
r0, [r1, #1]
r2, r0, r3
r4, r0, r5
r0, [r1]
r6, r7, r8
r4, r0, r5
r0, [r1]
r0, [r2]
r0, [r1]
r2, r3, r4, r0
r0, [r1]
r0, [r2]
r0, [r1]
r0, {r1-r2}
ADD
does not incur any interlocks:
STR
and
STM
instructions and for the accumulate
ARM DDI 0165B
ADD
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