SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 260
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 260 of 290
- Download datasheet (5Mb)
Debug in depth
C.7.2
C-20
Determining the system state
scanned in as the next instruction with bit 32 set HIGH.
After the system speed instructions are scanned into the instruction data bus and clocked
into the pipeline, the RESTART instruction must be loaded into the TAP controller. This
causes the ARM9E-S automatically to resynchronize back to CLK conditioned with
CLKEN when the TAP controller enters RUN-TEST/IDLE state, and executes the
instruction at system speed. Debug state is reentered once the instruction completes
execution, when the processor switches itself back to CLK conditioned with
DBGTCKEN. When the instruction completes, DBGACK is HIGH. At this point
To meet the dynamic timing requirements of the memory system, any attempt to access
system state must occur synchronously. Therefore, the ARM9E-S must be forced to
synchronize back to system speed. Bit 32 of scan chain 1, SYSSPEED, controls this.
You can place a legal debug instruction onto the instruction data bus of scan chain 1
with bit 32 (the SYSSPEED bit) LOW. This instruction is then executed at debug speed.
To execute an instruction at system speed, a NOP (such as
INTEST can be selected in the TAP controller, and debugging can resume.
To determine if a system speed instruction has completed, the debugger must look at
SYSCOMP (bit 3 of the debug status register). The ARM9E-S must access memory
through the data data bus interface, as this access can be stalled indefinitely by
CLKEN. Therefore, the only way to determine if the memory access has completed is
to examine the SYSCOMP bit. When this bit is HIGH, the instruction has completed.
The state of the system memory can be fed back to the debug host by using system speed
load multiples and debug speed store multiples.
Instructions that can have the SYSSPEED bit set
There are restrictions on which instructions can have the SYSSPEED bit set. The valid
instructions on which to set this bit are:
•
•
•
•
When the ARM9E-S returns to debug state after a system speed access, the SYSSPEED
bit is set LOW. The state of this bit gives the debugger information about why the core
entered debug state the first time this scan chain is read.
loads
stores
load multiple
store multiple.
Copyright © 2000 ARM Limited. All rights reserved.
MOV R0, R0
ARM DDI 0165B
) must be
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