AD9257 Analog Devices, AD9257 Datasheet - Page 22

• Manufacturer Part Number: AD9257
• Description: Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

AD9257
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 55).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9257.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
A
) due only to aperture jitter (t
SNR Degradation = 20 log
130
120
110
100
90
80
70
60
50
40
30
1
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
Figure 55. Ideal SNR vs. Input Frequency and Jitter
AN-501
ANALOG INPUT FREQUENCY (MHz)
Application Note and the
10
0.125ps
10
0.25ps
J
0.5ps
1.0ps
2.0ps
) can be calculated by
⎛
⎜
⎜
⎝
2
π
×
1
f
100
A
×
t
J
⎞
⎟
⎟
⎠
AN-756
16 BITS
14 BITS
12 BITS
1000
Rev. 0 | Page 22 of 40
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 56, the power dissipated by the
proportional to its sample rate. The digital power dissipation
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.
The
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 1 mW. During power-down, the output
drivers are placed in a high impedance state. Asserting the
PDWN pin low returns the
mode. Note that PDWN is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to
normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down cycles
result in proportionally shorter wake-up times. When using the
SPI port interface, the user can place the ADC in power-down
mode or standby mode. Standby mode allows the user to keep
the internal reference circuitry powered when faster wake-up
times are required. See the Memory Map section for more
details on using these features.
AD9257
400
350
300
250
200
150
Figure 56. Analog Core Power vs. f
10
is placed in power-down mode either by the SPI
15
20
20MSPS
25
SAMPLE RATE (MSPS)
30
AD9257
40MSPS
35
40
to its normal operating
50MSPS
SAMPLE
45
for f
50
65MSPS
IN
Data Sheet
= 9.7 MHz
55
80MSPS
AD9257
60
65
is