AD9257 Analog Devices, AD9257 Datasheet - Page 31

• Manufacturer Part Number: AD9257
• Description: Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

Data Sheet
MEMORY MAP REGISTER TABLE
The
therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3
and Bit 4 are set to 1. When Register 0x00, Bit 5 is set high, the
Table 17. Memory Map Register Table
Reg.
Addr.
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Device Index and Transfer Registers
0x04
0x05
0xFF
Global ADC Functions
0x08
0x09
AD9257
Register Name
SPI port
configuration
Chip ID (global)
Chip grade
(global)
Device Index 2
Device Index 1
Transfer
Power modes
(global)
Clock (global)
uses a 3-wire interface and 16-bit addressing and,
Bit 7
(MSB)
0 = SDO
active
Open
Open
Open
Open
Open
Open
Bit 6
LSB first
Open
Open
Open
Open
Open
Speed grade ID, Bits[6:4]
001 = 40 MSPS
011 = 65 MSPS
AD9257
Bit 5
Soft reset
Open
Clock
Channel
DCO
Open
External
power-
down pin
function
0 = full
power-
down
1 =
standby
Open
0x92 = octal 14-bit, 40 MSPS/65 MSPS serial LVDS
Rev. 0 | Page 31 of 40
8-bit chip ID, Bits[7:0]
Open
Open
Bit 4
1 =
16-bit
address
Clock
Channe
l FCO
Open
Open
Bit 3
1 = 16-bit
address
Open
Data
Channel H
Data
Channel D
Open
Open
Open
SPI enters a soft reset, where all of the user registers revert to
their default values and Bit 2 is automatically cleared.
Bit 2
Soft reset
Open
Data
Channel G
Data
Channel C
Open
Open
Open
Bit 1
LSB first
Open
Data
Channel F
Data
Channel B
Open
Open
01 = full power-down
Internal power-down
10 = standby
11 = reset
00 = chip run
mode
Open
Bit 0 (LSB)
0 = SDO
active
Duty cycle
stabilize
0 = off
1 = on
Data
Channel E
Data
Channel A
Initiate
override
Default
Value
(Hex)
0x18
Read
only
0x92
Read
only
0xF
0x3F
0x00
0x00
0x01
AD9257
Comments
The nibbles
are mirrored
so that LSB
or MSB first
mode registers
correctly. The
default for the
ADCs is 16-bit
mode.
Unique chip ID
that is used to
differentiate
devices; read
only.
Unique
speed grade
ID used to
differentiate
graded
devices.
Read only.
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default
is all devices
on chip.
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default
is all devices
on chip.
Set resolution/
sample rate
override.
Determines
various
generic modes
of chip
operation.
Turns duty
cycle stabilizer
on or off.