AD9257 Analog Devices, AD9257 Datasheet - Page 26

• Manufacturer Part Number: AD9257
• Description: Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

AD9257
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 2
of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value
is all 1s (see Table 12 for the initial values). The output is a
parallel representation of the serial PN9 sequence in MSB-first
format. The first output word is the first 14 bits of the PN9
sequence in MSB alig
Table 12. PN Sequence
Sequence
PN Sequence Short
PN Sequence Long
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 2
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
seed value is all 1s (see Table 12 for the initial values) and the
AD9257
The output is a parallel representation of the serial PN23 sequence
in MSB-first format. The first output word is the first 14 bits of the
PN23 sequence in MSB aligned format.
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
SDIO/DFS Pin
For applications that do not require SPI mode operation, the
CSB pin is tied to AVDD, and the SDIO/DFS pin controls the
output data format select according to Table 13.
Table 13. Output Data Format Select Pin Settings
DFS Pin Voltage
AVDD
GND (Default)
inverts the bit stream with relation to the ITU standard.
ned form.
Initial
Value
0x1FE0
0x1FFF
Output Mode
Twos complement
Offset binary
First Three Output Samples
(MSB First) Twos Complement
0x1DF1, 0x3CC8, 0x294E
0x1FE0, 0x2001, 0x1C00
9
23
− 1 or 511 bits. A description
− 1 or 8,388,607 bits. A
Rev. 0 | Page 26 of 40
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test pattern
if it and the CSB pin are both held high during device power-up.
When SCLK/DTP is tied to AVDD, the ADC channel outputs
shift out the following pattern: 10 0000 0000 0000. The FCO and
DCO function normally while all channels shift out the repeatable
test pattern. This pattern allows the user to perform timing
alignment adjustments among the FCO, DCO, and output data.
This pin has an internal 30 kΩ resistor to GND. It can be left
unconnected for normal operation.
Table 14. Digital Test Pattern Pin Settings
Selected DTP
Normal Operation
DTP
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map section
for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that
do not require SPI mode operation. Tying CSB high causes
all SCLK and SDIO information to be ignored.
RBIAS Pin
To set the internal core bias current of the ADC, place a
10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin.
DTP Voltage
No connect
AVDD
Resulting D± x
Normal operation
10 0000 0000 0000
Data Sheet