AD9628 Analog Devices, AD9628 Datasheet - Page 30

• Manufacturer Part Number: AD9628
• Description: 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9628

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip,SE-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9628
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNR
jitter (t
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 59.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9628.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
See the
Note available on
CHANNEL/CHIP SYNCHRONIZATION
The
synchronization options for synchronizing sample clocks
across multiple ADCs. The input clock divider can be enabled
to synchronize on a single occurrence of the SYNC signal or on
every occurrence. The SYNC input is internally synchronized
to the sample clock; however, to ensure that there is no timing
uncertainty between multiple parts, the SYNC input signal should
be externally synchronized to the input clock signal, meeting the
setup and hold times shown in Table 5. Drive the SYNC input
using a single-ended CMOS-type signal.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 60, the analog core power dissipated by
the
power dissipation of the CMOS outputs are determined
80
75
70
65
60
55
50
45
AD9628
AD9628
SNR
1
JRMS
AN-501
HF
) can be calculated by
= −10 log[(2π × f
is proportional to its sample rate. The digital
has a SYNC input that offers the user flexible
Figure 59. SNR vs. Input Frequency and Jitter
Application Note and the
www.analog.com
LF
) at a given input frequency (f
10
FREQUENCY (MHz)
INPUT
× t
for more information.
JRMS
)
AN-756
100
2
+ 10
3.0ps
(
−
SNR
Application
INPUT
0.05ps
0.2ps
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
LF
/
10
) due to
)
]
1k
Rev. 0 | Page 30 of 44
primarily by the strength of the digital drivers and the load
on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
where N is the number of output bits (26, in the case of the
AD9628).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 60 was
taken in CMOS mode using the same operating conditions as those
used for the power supplies and power consumption specifications
in Table 1 with a 5 pF load on each output driver.
100
Figure 60. AD9628-125 Power and Current vs. Clock Rate (1.8 V CMOS
Figure 61. AD9648-105 Power and Current vs. Clock Rate (1.8 V CMOS
90
80
70
60
50
40
30
20
10
90
80
70
60
50
40
30
20
10
I
0
0
DRVDD
5
5
= V
I
DRVDD
CLK
25
DRVDD
25
/2. In practice, the DRVDD current is estab-
× C
ENCODE RATE (MSPS)
45
ENCODE RATE (MSPS)
LOAD
45
Output Mode)
Output Mode)
× f
CLK
65
65
× N
TOTAL POWER
I
TOTAL POWER
I
DRVDD
AVDD
85
I
AVDD
85
105
105
125
200
180
160
140
120
100
80
60
40
240
190
140
90
40