AD9628 Analog Devices, AD9628 Datasheet - Page 37

• Manufacturer Part Number: AD9628
• Description: 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9628

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip,SE-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Addr
(Hex)
0x0C
0x0D
0x0E
0x10
0x14
0x15
0x16
0x17
0x18
0x19
Register
Name
Enhance-
ment
control
(global)
Test mode
(local)
BIST enable
(global)
Customer
offset
adjust
(local)
Output
mode
Output
adjust
Clock phase
control
(global)
Output
delay
(global)
VREF select
(global)
User
Pattern 1
LSB (global)
Bit 7
(MSB)
Open
User test mode
control
00 = single pattern
mode
01 = alternate
continuous/repeat
pattern mode
10 = single once
pattern mode
11 = alternate once
pattern mode
Open
Output port logic type
(global)
00 = CMOS, 1.8 V
10 = LVDS, ANSI
11 = LVDS, reduced
range
Open
Invert
DCO
clock
0 = not
inverted
1 =
inverted
DCO
Clock
delay
0 =
disabled
1 =
enabled
Open
B7
Bit 6
Open
Open
Open
Open
Open
Open
B6
Bit 5
Open
Reset PN
long gen
Open
Output
interleave
enable
(global)
Open
Data delay
0 =
disabled
1 =
enabled
Open
B5
CMOS 1.8 V DCO drive
strength
00 = 1×
01 = 2×
10 = 3×
11 = 4×
Offset adjust in LSBs from +127 to −128
Bit 4
Open
Reset PN
short gen
Open
Output
port
disable
(local)
Open
Open
Open
B4
(twos complement format)
Rev. 0 | Page 37 of 44
Bit 3
Open
Open
Open
(global)
Open
Open
Open
Open
B3
Output test mode
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN long sequence
0110 = PN short sequence
0111 = one/zero word toggle
1000 = user test mode
1111 = ramp output
Chop
0 =
1 =
Bit 2
disabled
enabled
Initialize
BIST
sequence
Output
invert
(local)
Open
Input clock divider phase adjust
relative to the encode clock
000 = no delay
001 = one input clock cycle
010 = two input clock cycles
011 = three input clock cycles
100 = four input clock cycles
101 = five input clock cycles
110 = six input clock cycles
111 = seven input clock cycles
B2
Internal V
Delay selection
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
000 = 1.0 V p-p
001 = 1.14 V p-p
010 = 1.33 V p-p
011 = 1.6 V p-p
100 = 2.0 V p-p
Bit 1
Open
Open
Output format
00 = offset binary
01 = twos complement
10 = Gray code
B1
REF
digital adjustment
CMOS 1.8 V data
drive strength
00 = 1×
01 = 2×
10 = 3×
11 = 4×
Open
Bit 0
(LSB)
BIST enable
B0
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x00
AD9628
Comments
Chop mode
enabled if Bit
2 is enabled.
When this
register is
set, the test
data is
placed on
the output
pins in place
of normal
data
Configures
the outputs
and the
format of the
data
Determines
CMOS
output drive
strength
properties
Allows
selection of
clock delays
into the
input clock
divider
This sets the
fine output
delay of the
output clock
but does not
change
internal
timing
Select and/or
adjust V
User-defined
Pattern 1 LSB
REF