AD6659 Analog Devices, AD6659 Datasheet - Page 20

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6659
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD6659 sample clock inputs,
CLK+ and CLK−, with a differential signal. The signal is typically
ac-coupled into the CLK+ and CLK− pins via a transformer or
capacitors. These pins are biased internally (see Figure 36) and
require no external bias.
Clock Input Options
The AD6659 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 37 and Figure 38 show two preferred methods for clocking
the AD6659 (at clock rates up to 480 MHz before the internal
CLK divider). A low jitter clock source is converted from a
single-ended signal to a differential signal using either an RF
transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 480 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD6659 to approximately
0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD6659 while preserving
the fast rise and fall times of the signal that are critical to a low
jitter performance.
CLOCK
INPUT
Figure 37. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLK+
50Ω
0.1µF
Figure 36. Equivalent Clock Input Circuit
2pF
100Ω
ADT1-1WT, 1:1 Z
Mini-Circuits
XFMR
0.1µF
AVDD
0.9V
®
0.1µF
0.1µF
SCHOTTKY
HSMS2822
DIODES:
2pF
CLK–
CLK+
CLK–
ADC
Rev. | Page 20 of 40
CLOCK
1
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 39. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517
excellent jitter performance.
Another option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 40. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 41).
CLOCK
CLOCK
CLOCK
CLOCK
50Ω RESISTOR IS OPTIONAL.
INPUT
INPUT
INPUT
INPUT
INPUT
CLOCK
INPUT
Figure 41. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50kΩ
50kΩ
Figure 38. Balun-Coupled Differential Clock (Up to 480 MHz)
Figure 40. Differential LVDS Sample Clock (Up to 480 MHz)
Figure 39. Differential PECL Sample Clock (Up to 480 MHz)
50Ω
0.1µF
1
50Ω
1nF
0.1µF
0.1µF
50kΩ
1nF
0.1µF
0.1µF
V
50kΩ
CC
1kΩ
1kΩ
LVDS DRIVER
PECL DRIVER
CMOS DRIVER
AD951x
AD951x
AD951x
240Ω
0.1µF
0.1µF
SCHOTTKY
HSMS2822
DIODES:
OPTIONAL
240Ω
100Ω
0.1µF
100Ω
0.1µF
0.1µF
100Ω
clock drivers offer
0.1µF
0.1µF
0.1µF
CLK+
CLK–
ADC
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
ADC
ADC
ADC