AD6659 Analog Devices, AD6659 Datasheet - Page 31

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table (see Table 17) has
eight bit locations. The memory map is roughly divided into
four sections: the chip configuration registers (Address 0x00 to
Address 0x02); the device index and transfer registers (Address 0x05
and Address 0xFF); the program registers, including setup, control,
and test (Address 0x08 to Address 0x2E); and the digital feature
control registers (Address 0x100 to Address 0x11E).
Table 17 documents the default hexadecimal value for each
hexadecimal address shown. The column with the heading
Bit 7 (MSB) is the start of the default hexadecimal value given.
For example, Address 0x05, the channel index register, has a hex-
adecimal default value of 0x03. This means that in Address 0x05
Bits[7:2] = 0, and the remaining Bits[1:0] = 1. This setting is the
default channel index setting. The default value results in both
ADC channels receiving the next write command. For more
information on this function and others, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI. This
application note details the functions controlled by Register 0x00
to Register 0xFF. The remaining AD6659 specific registers,
Register 0x100 through Register 0x11E, are documented in the
Memory Map Register Descriptions section following Table 17.
OPEN LOCATIONS
All address and bit locations excluded in the SPI map are not
currently supported for this device. Unused bits of a valid
address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x05). If the entire address location
is open, it is omitted from the SPI map (for example, Address 0x13)
and should not be written.
DEFAULT VALUES
After the AD6659 is reset, critical registers are loaded with default
values. The default values for the registers are given in the
memory map register table (see Table 17).
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Logic Levels
An explanation of logic level terminology follows:
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•
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simulta-
neously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and then the bit autoclears.
Channel-Specific Registers
Some channel setup functions can be programmed differently
for each channel. In these cases, channel address locations are
internally duplicated for each channel. These registers and bits
are designated in the memory map register table as local. These
local registers and bits can be accessed by setting the appropriate
Channel A (Bit 0) or Channel B (Bit 1) bit in Register 0x05.
If both bits are set, the subsequent write affects the registers of both
channels. In a read cycle, set only Channel A or Channel B to read
one of the two registers. If both bits are set during an SPI read
cycle, the part returns the value for Channel A. Registers and
bits designated as global in the memory map register table (see
Table 17) affect the entire part or the channel features for which
independent settings are not allowed between channels. The
settings in Register 0x05 do not affect the global registers and bits.
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit. ”
“Bit is cleared” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit. ”
AD6659