AD6659 Analog Devices, AD6659 Datasheet - Page 33

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Addr
(Hex)
0x0D
0x0E
0x10
0x14
0x15
0x16
0x17
0x19
Register Name
Test mode (local)
BIST enable
Offset adjust
(local)
Output mode
Output adjust
Output phase
Output delay
USER_PATT1_LSB
Bit 7
(MSB)
Open
DCO
output
polarity
0 =
normal
1 =
inverted
(local)
Enable
DCO
delay
B7
10 = single once
00 = 3.3 V CMOS
10 = 1.8 V CMOS
3.3 V DCO drive
User test mode
01 = alternate
11 = alternate
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
00 = 1 stripe
00 = single
strength
(default)
(local)
once
Bit 6
Offset adjust in LSBs from +127 to −128 (twos complement format)
Open
Open
Open
B6
Bit 5
Reset PN
long gen
Open
Output mux
enable
(interleaved)
Open
Enable data
delay
B5
10 = 3 stripes (default)
8-bit Device Offset Adjustment[7:0] (local)
1.8 V DCO drive
01 = 2 stripes
11 = 4 stripes
00 = 1 stripe
strength
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Bit 4
Reset
PN
short
gen
Open
Output
disable
(local)
Open
Open
B4
Bit 3
Open
Open
Open
Open
B3
3.3 V data drive
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
00 = 1 stripe
strength
(default)
0100 = alternating checkerboard
Output test mode [3:0] (local)
1100 = mixed bit frequency
0111 = 1-/0-word toggle
0101 = PN 23 sequence
Bit 2
BIST
INIT
Output
invert
(local)
0001 = midscale short
0110 = PN 9 sequence
1001 = 1-/0-bit toggle
B2
1011 = one bit high
0000 = off (default)
0011 = negative FS
Input Clock Phase Adjust[2:0]
0010 = positive FS
1000 = user input
clock cycles of phase delay)
1010 = 1× sync
(Value is number of input
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
001 = 1 input clock cycle
DCO/Data Delay[2:0]
000 = no delay
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
Bit 1
Open
B1
00 = offset binary
11 = offset binary
10 = gray code
1.8 V data drive
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
complement
00 = 1 stripe
01 = twos
(default)
strength
(local)
Bit 0
(LSB)
BIST
enable
B0
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x22
0x00
0x00
0x00
Comments
When set, the test
data is placed on
the output pins in
place of normal
data
When Bit 0 is set,
the BIST function is
initiated
Device offset trim
Configures the
outputs and the
format of the data
Determines CMOS
output drive
strength properties
On devices that use
global clock divide,
this register
determines which
phase of the
divider output is
used to supply the
output clock;
internal latching is
unaffected
Sets the fine output
delay of the output
clock but does not
change internal
timing
User-defined
Pattern 1, LSB
AD6659