AD7192 Analog Devices, AD7192 Datasheet
AD7192
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AD7192 Summary of contents
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... Data acquisition Medical and scientific instrumentation GENERAL DESCRIPTION The AD7192 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC ...
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... AD7192 TABLE OF CONTENTS Features .............................................................................................. 1 Interface ............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ..................................................................... 7 Circuit and Timing Diagrams ..................................................... 7 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 RMS Noise and Resolution ............................................................ 14 4 Sinc Chop Disabled ...
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... Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. dB min 50 Hz output data rate, REJ60 50 ± 1 Hz, 60 ± 1 Hz. dB min 50 Hz output data rate, 50 ± 1 Hz. dB min 60 Hz output data rate, 60 ± 1 Hz. Rev Page AD7192 1 4 filter 3 filter 4 filter 3 3 ...
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... AD7192 Parameter AD7192B External Clock @ 50 Hz 120 120 @ 60 Hz 120 3 Sinc Filter Internal Clock @ 50 Hz External Clock @ 50 Hz 100 ANALOG INPUTS Differential Input Voltage Ranges ± V ± (AV 2 Absolute AIN Voltage Limits Unbuffered Mode AGND − ...
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... V min/V max μA max − 0.6 V min DD V max V min V max μA max pF typ Rev Page AD7192 1 Test Conditions/Comments External clock. Internal clock. Applies after user calibration at 25°C. Bipolar mode. Continuous current. Analog inputs must be buffered and chop disabled 100 μ ...
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... AD7192 Parameter AD7192B 2 SYSTEM CALIBRATION Full-Scale Calibration Limit 1.05 × FS Zero-Scale Calibration Limit −1.05 × FS Input Span 0.8 × FS 2.1 × POWER REQUIREMENTS Power Supply Voltage AV − AGND 3/5. − DGND 2.7/5.25 DD Power Supply Currents AI Current 0.6 DD 0.85 3.2 3.6 4 Current 0.4 DD 0.6 1.5 I (Power-Down Mode Temperature range: −40°C to +105°C. ...
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... SOURCE 100µA WITH DV = 3V) DD Figure 2. Load Circuit for Timing Characterization Rev Page unless otherwise noted (10 and timed from a voltage level of 1 limits 5V 5V, DD AD7192 4 ...
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... AD7192 DOUT/RDY (O) SCLK (I) SCLK ( MSB INPUT OUTPUT Figure 3. Read Cycle Timing Diagram CS ( DIN (I) MSB LSB I = INPUT OUTPUT Figure 4. Write Cycle Timing Diagram Rev Page LSB ...
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... THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type + 0.3 V 24-Lead TSSOP ESD CAUTION + 0 0 Rev Page AD7192 θ θ Unit JA JC 128 42 °C/W ...
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... Master Clock Signal for the Device. The AD7192 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7192 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected ...
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... Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7192 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state low ...
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... AD7192 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,884 8,388,882 8,388,880 8,388,878 8,388,876 8,388,874 8,388,872 8,388,870 8,388,868 8,388,866 0 200 400 600 SAMPLE Figure 6. Noise ( Output Data Rate = 4.7 Hz, REF DD Gain = 128, Chop Disabled, Sinc 200 150 100 50 0 8,388,865 8,388,869 8,388,873 8,388,877 CODE Figure 7. Noise Distribution Histogram (V Output Data Rate = 4 ...
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... Rev Page AD7192 –40 – 100 TEMPERATURE (°C) –40 – 100 TEMPERATURE (°C) Figure 16. Gain Error (Gain = 1) –40 –20 ...
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... RMS NOISE AND RESOLUTION The AD7192 has a choice of two filter types: sinc In addition, the AD7192 can be operated with chop enabled or chop disabled. The following tables show the rms noise of the AD7192 for some of the output data rates and gain settings with chop disabled 4 3 ...
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... Gain of 32 Gain of 64 Gain of 128 24 (21.5) 23 (20.5) 22.5 (20) 23.5 (21) 23 (20.5) 22 (19.5) 23.5 (21) 22.5 (20) 22 (19.5) 22 (19.5) 21.5 (19) 21 (18.5) 21.5 (19) 21.5 (19) 20.5 (18) 21.5 (19) 21 (18.5) 20 (17.5) 21.5 (19) 21 (18.5) 20 (17.5) 21 (18.5) 20.5 (18) 19.5 (17) 20 (17.5) 19.5 (17) 18.5 (16) 17 (14.5) 17 (14.5) 17 (14.5) 14 (11.5) 14 (11.5) 14 (11.5) AD7192 1 ...
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... AD7192 4 SINC CHOP ENABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Output Filter Word Data Rate Settling (Decimal) (Hz) Time (ms) 1023 1.175 1702 640 1.875 1067 480 2.5 800 96 12.5 160 80 15 133 40 30 66.7 32 37.5 53 26.7 5 240 8.33 2 600 3.33 1 1200 1.67 Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate ...
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... Gain of 32 Gain (22) 23.5 (21) 24 (21.5) 23.5 (21) 24 (21.5) 23 (20.5) 22.5 (20) 22 (19.5) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 19.5 (17) 17.5 (15) 17.5 (15) 14.5 (12) 14.5 (12) AD7192 1 Gain of 128 23 (20.5) 22.5 (20) 22.5 (20) 21.5 (19) 21 (18.5) 20.5 (18) 20.5 (18) 20 (17.5) 18.5 (16) 17.5 (15) 14.5 (12) ...
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... AD7192 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages. In the following descriptions, “set” implies a Logic 1 state and “cleared” implies a Logic 0 state, unless otherwise noted. COMMUNICATIONS REGISTER (RS2, RS1, RS0 = The communications register is an 8-bit write-only register ...
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... SR3 SR2 PARITY(0) 0(0) CHD2(0) MR20 MR19 MR18 DAT_STA(0) CLK1(1) CLK0(0) MR12 MR11 MR10 CLK_DIV(0) SINGLE(0) REJ60(0) MR4 MR3 MR2 FS4(0) FS3(0) FS2(0) Rev Page AD7192 SR1 SR0 CHD1(0) CHD0(0) MR17 MR16 0 0 MR9 MR8 FS9(0) FS8(0) MR1 MR0 FS1(0) FS0(0) ...
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... MR19, MR18 CLK1, CLK0 These bits are used to select the clock source for the AD7192. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7192 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7192 ...
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... Power-down mode. In power-down mode, all AD7192 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7192 for settling reasons. The external crystal, if selected, remains active. ...
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... CON15 to CON8 CH7 to CH0 Channel select bits. These bits are used to select which channels are enabled on the AD7192 (see Table 20). Several channels can be selected, and the AD7192 automatically sequences them. The conversion on each channel requires the complete settling time. When performing calibrations or when accessing the calibration registers, only one channel can be selected ...
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... Temperature sensor AIN2 AIN1 AIN2 AIN3 AIN4 ID REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0xX0) The identification number for the AD7192 is stored in the ID register. This is a read-only register. Rev Page Negative Input Status Register AIN(−) Bits CHD[2:0] AIN2 000 ...
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... The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7192 must be placed in power- down mode or idle mode when writing to the offset register. Table 21 outlines the bit designations for the GPOCON register. ...
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... IN+ OUT+ OUT– IN– OVERVIEW The AD7192 is an ultralow noise ADC that incorporates a Σ-Δ modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as those in pressure transducers, weigh scales, and strain gage applications. The part can be configured to have two differential inputs or four pseudo differential inputs that can be buffered or unbuffered ...
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... AD7192 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY (Hz) 3 Figure 20. Sinc Filter Response (50 Hz Output Data Rate) 4 The sinc filter provides 50 Hz (±1 Hz) rejection in excess of 120 dB, assuming a stable master clock, and the sinc a rejection of 100 dB. The stop-band attenuation is, typically, ...
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... For example, when zero latency is not enabled, the AD7192 has a noise-free resolution of 18.5 bits when the output data rate and the gain is set to 128. When zero latency is enabled, the ADC has a resolution of 17 ...
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... The AD7192 takes care of this: when a channel is selected, the modulator and filter are reset and the RDY pin is taken high. The AD7192 then allows the complete settling time to generate the first conversion. RDY goes low only when a valid conversion is available. The AD7192 then selects the next enabled channel and converts on that channel ...
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... The serial interface can be reset by writing a series the DIN input Logic 1 is written to the AD7192 DIN line for at least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system ...
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... AD7192 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7192 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete low, the DOUT/ RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register ...
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... Continuous Read Rather than write to the communications register each time a conversion is complete to access the data, the AD7192 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 to the communi- cations register, the user need only apply the appropriate ...
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... Hz, which is equivalent to 22.5 bits of effective resolution or 20 bits of noise-free resolution. The AD7192 can be programmed to have a gain 16, 32, 64, and 128 using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 19. 2.5 V and the bipolar ranges are from ± ...
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... REFINx(−) pins is between 0.3 V and 0.6 V, the AD7192 detects that it no longer has a valid reference. In this case, the NOREF bit of the status register is set the AD7192 is performing normal conversions and the NOREF bit becomes active, the conversion result is all 1s. ...
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... AD7192 RESET The circuitry and serial interface of the AD7192 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. A reset is automatically performed on power-up. When a reset is initiated, the user must allow a period of 500 μ ...
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... The gain error of the AD7192 is factory calibrated at a gain of 1 with power supply at ambient temperature. Following this calibration, the gain error is 0.001%, typically Table 23 shows the typical uncalibrated gain error for the different gain settings ...
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... AD7192 to prevent noise coupling. The power supply lines to the AD7192 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals ...
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... WEIGH SCALES Figure 32 shows the AD7192 being used in a weigh scale application. The load cell is arranged in a bridge network and gives a differential output voltage between its OUT+ and OUT– ...
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... AD7192 OUTLINE DIMENSIONS 0.15 0.05 ORDERING GUIDE Model Temperature Range AD7192BRUZ 1 –40°C to +105°C 1 AD7192BRUZ-REEL –40°C to +105° RoHS Compliant Part. 7.90 7.80 7. 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.30 0.20 SEATING 0.19 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP] ...
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... NOTES Rev Page AD7192 ...
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... AD7192 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07822-0-5/09(A) Rev Page ...