AD7192 Analog Devices, AD7192 Datasheet - Page 7
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
AD7192
Manufacturer Part Number
AD7192
Description
4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA
Manufacturer
Analog Devices
Datasheet
1.AD7192.pdf
(40 pages)
Specifications of AD7192
Resolution (bits)
24bit
# Chan
4
Sample Rate
4.8kSPS
Interface
Ser,SPI
Analog Input Type
Diff-Bip,Diff-Uni,SE-Bip,SE-Uni
Ain Range
± (Vref/Gain)
Adc Architecture
Sigma-Delta
Pkg Type
SOP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD7192BRUZ
Manufacturer:
ADI
Quantity:
1 000
Company:
Part Number:
AD7192BRUZ
Manufacturer:
AD
Quantity:
1 831
Company:
Part Number:
AD7192BRUZ
Manufacturer:
ADI
Quantity:
325
Part Number:
AD7192BRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD7192BRUZ-REEL
Manufacturer:
ADI
Quantity:
1 000
TIMING CHARACTERISTICS
AV
Table 2.
Parameter
t
t
READ OPERATION
WRITE OPERATION
1
2
3
4
5
6
CIRCUIT AND TIMING DIAGRAMS
3
4
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figure 3 and Figure 4.
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V
The SCLK active edge is the falling edge of SCLK.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.
t
t
t
t
t
t
t
t
t
DD
1
2
5
6
7
8
9
10
11
3
5, 6
= 3 V to 5.25 V, DV
Limit at T
100
100
0
60
80
0
60
80
10
80
0
10
0
30
25
0
DD
= 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV
MIN
, T
MAX
(B Version)
OUTPUT
Figure 2. Load Circuit for Timing Characterization
PIN
TO
50pF
Rev. A | Page 7 of 40
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
I
100µA WITH DV
I
100µA WITH DV
SINK
SOURCE
(1.6mA WITH DV
(200µA WITH DV
1.6V
DD
DD
Conditions/Comments
SCLK high pulse width
SCLK low pulse width
CS falling edge to DOUT/RDY active time
DV
DV
SCLK active edge to data valid delay
DV
DV
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high
CS falling edge to SCLK active edge setup time
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
R
= t
= 3V)
= 3V)
DD
DD
DD
DD
F
DD
= 5 ns (10% to 90% of DV
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
= 5V,
DD
= 5V,
1, 2
DD
) and timed from a voltage level of 1.6 V.
OL
DD
or V
, unless otherwise noted.
OH
4
limits.
4
AD7192