AD7366-5 Analog Devices, AD7366-5 Datasheet - Page 22

• Manufacturer Part Number: AD7366-5
• Description: True Bipolar Input, 12-Bit, 2-Channel, Simultaneous Sampling SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7366-5

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip 10V,Bip 5.0V,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7366-5/AD7367-5
SERIAL INTERFACE
Figure 25 and Figure 26 show the detailed timing diagrams for
serial interfacing to the AD7366-5 and the AD7367-5, respectively.
On the falling edge of CNVST , the AD7366-5/AD7367-5 simulta-
neously converts the selected channels. These conversions are
performed using the on-chip oscillator. After the falling edge of
CNVST , the BUSY signal goes high, indicating the conversion has
started. It returns low once the conversion has been completed.
The data can now be read from the
CS and SCLK signals are required to transfer data from the
AD7366-5/AD7367-5. The parts have two output pins corre-
sponding to each ADC. Data can be read from the AD7366-5/
AD7367-5 using both D
output pin of the user’s choice can be used. The SCLK input signal
provides the clock source for the serial interface. The CS goes
low to access data from the AD7366-5/AD7367-5. The falling edge
of CS takes the bus out of three-state and clocks out the MSB of
the conversion result. The data stream consists of 12 bits of data
for the AD7366-5 and 14 bits of data for the AD7367-5, MSB first.
The first bit of the conversion result is valid on the first SCLK
falling edge after the CS falling edge. The subsequent 11-bits/
13-bits of data for the AD7366-5/AD7367-5, respectively, are
clocked out on the falling edge of the SCLK signal. A minimum
of 12 clock pulses must be provided to the AD7366-5 to access
each conversion result, while a minimum of 14 clock pulses must
be provided to the AD7367-5 to access the conversion result.
Figure 25 shows how a 12 SCLK read is used to access the
conversion results, while Figure 26 illustrates the case for the
AD7367-5 with a 14 SCLK read.
D
D
D
D
SCLK
OUT
OUT
SCLK
OUT
OUT
CS
CS
A
B
A
B THREE-
STATE
THREE-
STATE
DB13
DB11
OUT
1
1
t
t
4
4
A and D
DB12
DB10
2
2
D
OUT
DB11
DB9
OUT
B. Alternatively, a single
pins.
3
3
Figure 25. Serial Interface Timing Diagram for the AD7366-5
Figure 26. Serial Interface Timing Diagram for the AD7367-5
DB10
DB8
4
4
t
t
5
5
t
t
8
8
5
5
Rev. A | Page 22 of 28
t
t
6
6
On the rising edge of CS , the conversion is terminated, and D
and D
but is instead held low for a further 12 SCLK cycles for the
AD7366-5 or 14 SCLK cycles for the AD7367-5 on either D
or D
This is illustrated in
D
three-state on the rising edge of
If the falling edge of SCLK coincides with the falling edge of CS ,
the falling edge of SCLK is not acknowledged by the AD7366-5/
AD7367-5, and the next falling edge of the SCLK is the first
registered after the falling edges of the CS .
The CS pin can be brought low before the BUSY signal goes low,
indicating the end of a conversion. Once CS is at a logic low state,
the data bus is brought out of three-state. This feature can be
utilized to ensure that the MSB is valid on the falling edge of
BUSY by bringing CS low a minimum of t
signal goes low. The dotted
illustrates this.
Alternatively, the CS pin can be tied to a low logic state continu-
ously. In this case, the D
data bus is continuously active. Under these conditions, the MSB
of the conversion result for the AD7366-5/AD7367-5 is available
on the falling edge of the BUSY signal. The next most significant
bit is available on the first SCLK falling edge after the BUSY
signal has gone low. This mode of operation enables the user to
read the MSB as soon as it is made available by the converter.
OUT
OUT
A is shown. In this case, the D
DB2
t
DB2
t
7
OUT
7
B, the data from the other ADC follows on that D
B go back into three-state. If CS is not brought high,
DB1
DB1
Figure 27
DB0
DB0
OUT
t
t
9
9
CS line
pins never enter three-state, and the
14
12
and
CS .
THREE-STATE
THREE-STATE
Figure 28
OUT
in
Figure 22
line in use goes back into
4
ns before the BUSY
where the case for
and
Figure 23
OUT
OUT
OUT
pin.
A
A