AD7324 Analog Devices, AD7324 Datasheet - Page 17

• Manufacturer Part Number: AD7324
• Description: Software Selectable True Bipolar Input, 4-Channel, 12-Bit Plus Sign A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7324

• Resolution (bits): 13bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: Bip (Vref),Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 2.5V,Bip 5.0V,Uni (Vref) x 4,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

Figure 25 shows the differential configuration during the
acquisition phase. For the conversion phase, SW3 opens and
SW1 and SW2 move to Position B (Figure 26). The output
impedances of the source driving the V
be matched; otherwise, the two inputs have different settling
times, resulting in errors.
Output Coding
The AD7324 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When
operating in sequence mode, the output coding for each
channel in the sequence is the value written to the coding bit
during the last write to the control register.
Transfer Functions
The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is
dependent on the analog input range selected.
Table 7. LSB Sizes for Each Analog Input Range
Input Range
±10 V
±5 V
±2.5 V
0 V to +10 V
Figure 25. ADC Differential Configuration During Acquisition Phase
Figure 26. ADC Differential Configuration During Conversion Phase
V
V
V
V
IN
IN
IN
IN
+
–
+
–
B
B
B
B
A
A
V
A
A
V
REF
REF
Full-Scale Range/8192 Codes
20 V
10 V
5 V
10 V
SW1
SW2
SW1
SW2
C
C
C
C
S
S
S
S
SW3
SW3
COMPARATOR
COMPARATOR
IN
+ and V
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
CONTROL
CONTROL
LOGIC
LOGIC
DAC
DAC
DAC
DAC
IN
− pins must
LSB Size
2.441 mV
1.22 mV
0.61 mV
1.22 mV
Rev. A | Page 17 of 36
The ideal transfer characteristic for the AD7324 when twos
complement coding is selected is shown in Figure 27. The ideal
transfer characteristic for the AD7324 when straight binary
coding is selected is shown in Figure 28.
ANALOG INPUT STRUCTURE
The analog inputs of the AD7324 can be configured as single-
ended, true differential, or pseudo differential via the control
register mode bits (see Table 10). The AD7324 can accept true
bipolar input signals. On power-up, the analog inputs operate as
four single-ended analog input channels. If true differential or
pseudo differential is required, a write to the control register is
necessary after power-up to change this configuration.
Figure 29 shows the equivalent analog input circuit of the
AD7324 in single-ended mode. Figure 30 shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
Figure 27. Twos Complement Transfer Characteristic (Bipolar Ranges)
Figure 28. Straight Binary Transfer Characteristic (Bipolar Ranges)
Figure 29. Equivalent Analog Input Circuit (Single-Ended)
000...001
000...000
100...010
100...001
100...000
000...010
000...001
000...000
011...111
011...110
111...110
111...000
011...111
111...111
111...111
–FSR/2 + 1LSB
AGND + 1LSB
V
IN
0
–FSR/2 + 1LSB
AGND + 1LSB
AGND – 1LSB
C1
ANALOG INPUT
ANALOG INPUT
V
V
DD
SS
D
D
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB
R1
UNIPOLAR RANGE
UNIPOLAR RANGE
C2
AD7324