AD7324 Analog Devices, AD7324 Datasheet - Page 31

• Manufacturer Part Number: AD7324
• Description: Software Selectable True Bipolar Input, 4-Channel, 12-Bit Plus Sign A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7324

• Resolution (bits): 13bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: Bip (Vref),Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 2.5V,Bip 5.0V,Uni (Vref) x 4,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

SERIAL INTERFACE
Figure 51 shows the timing diagram for the serial interface of
the AD7324. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7324 during a conversion.
The CS signal initiates the data transfer and the conversion
process. The falling edge of CS puts the track-and-hold into hold
mode and takes the bus out of three-state. Then the analog input
signal is sampled. Once the conversion is initiated, it requires
16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14
rising edge. On the 16
to three-state. If the rising edge of CS occurs before 16 SCLK cycles
have elapsed, the conversion is terminated, and the DOUT line
returns to three-state. Depending on where the CS signal is brought
high, the addressed register may be updated.
DOUT
SCLK
DIN
CS
THREE-
STATE
th
SCLK falling edge, the DOUT line returns
WRITE
ZERO
t
2
1
2 IDENTIFICATION BITS
t
ADD1
3
t
SEL1
9
REG
2
ADD0
SEL2
REG
Figure 51. Serial Interface Timing Diagram (Control Register Write)
3
SIGN
MSB
4
DB11
t
t
6
4
t
th
CONVERT
t
10
5
SCLK
t
DB10
7
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Data is clocked into the AD7324 on the SCLK falling edge. The
3 MSBs on the DIN line are decoded to select which register is
being addressed. The control register is a 12-bit register. If the
control register is addressed by the 3 MSBs, the data on the DIN
line is loaded into the control on the 15
sequence register or the range register is addressed, the data on
the DIN line is loaded into the addressed register on the 11
falling edge.
Conversion data is clocked out of the AD7324 on each SCLK
falling edge. Data on the DOUT line consists of a leading ZERO
bit, two channel identifier bits, a sign bit, and a 12-bit conversion
result. The channel identifier bits are used to indicate which
channel corresponds to the conversion result. The leading ZERO
bit is clocked out on the CS falling edge, and the first channel
identifier bit is clocked out on the first SCLK falling edge.
DB2
14
t
5
DB1
LSB
15
DB0
DON’T
CARE
16
THREE-STATE
t
8
t
QUIET
t
1
th
SCLK rising edge. If the
AD7324
th
SCLK