AD7934-6 Analog Devices, AD7934-6 Datasheet - Page 21

• Manufacturer Part Number: AD7934-6
• Description: 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7934-6

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

PARALLEL INTERFACE
The AD7934-6 has a flexible, high speed, parallel interface. This
interface is 12 bits wide and is capable of operating in either
word (W/ B tied high) or byte (W/ B tied low) mode. The
CONVST signal is used to initiate conversions and, when
operating in autoshutdown or autostandby mode, it is used to
initiate power-up.
A falling edge on the CONVST signal is used to initiate conver-
sions, and it also puts the ADC track-and-hold into track. Once
the CONVST signal goes low, the BUSY signal goes high for the
duration of the conversion. Between conversions, CONVST must
be brought high for a minimum time of t
the 14
aborted and the track-and-hold goes back into track.
th
falling edge of CLKIN; otherwise, the conversion is
TRACK/HOLD
DB0 TO DB11
DB0 TO DB11
INTERNAL
CONVST
CLKIN
BUSY
RD
CS
Figure 34. AD7934-6 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/ B = 1)
WITH CS AND RD TIED LOW
t
2
t
3
1
. This must occur after
1
2
THREE-STATE
OLD DATA
3
4
t
CONVERT
Rev. B | Page 21 of 28
5
12
A
At the end of the conversion, BUSY goes low and can be used to
activate an interrupt service routine. The CS and RD lines are
then activated in parallel to read the 12 bits of conversion data.
When power supplies are first applied to the device, a rising
edge on CONVST is necessary to put the track-and-hold into
track. The acquisition time of 125 ns minimum must be allowed
before CONVST is brought low to initiate a conversion. The
ADC then goes into hold on the falling edge of CONVST , and
back into track on the 13
When operating the device in autoshutdown or autostandby
mode, where the ADC powers down at the end of each
conversion, a rising edge on the CONVST signal is used to
power up the device.
13
t
B
10
t
9
14
t
20
t
13
t
12
t
DATA
DATA
ACQUISITION
t
1
th
rising edge of CLKIN (see Figure 34).
THREE-STATE
t
t
11
14
t
QUIET
AD7934-6