AD7934-6 Analog Devices, AD7934-6 Datasheet - Page 23

• Manufacturer Part Number: AD7934-6
• Description: 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7934-6

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

Writing Data to the AD7934-6
With W/ B tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7934-6. The DB8/HBEN pin assumes its DB8 function. Data
written to the AD7934-6 should be provided on the DB0 to
DB11 inputs, with DB0 being the LSB of the data-word. With
W/ B tied logic low, the AD7934-6 requires two write operations
to transfer a full 12-bit word. DB8/HBEN assumes its HBEN
function. Data written to the AD7934-6 should be provided on
the DB0 to DB7 inputs. HBEN determines whether the byte
written is high byte or low byte data. The low byte of the data-
word has DB0 being the LSB of the full data-word. For the high
byte write, HBEN should be high, and the data on the DB0
input should be Data Bit 8 of the 12-bit word.
Figure 36 shows the write cycle timing diagram of the AD7934-6.
When operating in word mode, the HBEN input does not exist,
and only one write operation is required to write the word of
data to the device. Data should be provided on DB0 to DB11.
DB0 TO DB7
HBEN/DB8
Figure 36. AD7934-6 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ B = 1)
Figure 37. AD7934-6 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ B = 0)
WR
CS
DB0 TO DB11
WR
CS
t
18
t
4
t
LOW BYTE
4
t
6
Rev. B | Page 23 of 28
t
7
t
5
t
19
t
6
t
DATA
t
8
7
When operating in byte mode, the two write cycles shown in
Figure 37 are required to write the full data-word to the
AD7934-6. In Figure 37, the first write transfers the lower eight
bits of the data-word from DB0 to DB7, and the second write
transfers the upper four bits of the data-word.
When writing to the AD7934-6, the top four bits in the high
byte must be 0s.
The data is latched into the device on the rising edge of WR . The
data needs to be set up a time, t
held for a time, t
signals are gated internally. CS and WR can be tied together as
the timing specification for t
CS and RD have not already been tied together).
t
17
t
8
t
t
5
18
8
, after the WR rising edge. The CS and WR
HIGH BYTE
t
19
4
, and t
7
, before the WR rising edge and
5
is 0 ns minimum (assuming
AD7934-6