AD7854 Analog Devices, AD7854 Datasheet - Page 17

• Manufacturer Part Number: AD7854
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Parallel Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7854

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

REV. B
POWER-DOWN OPTIONS
The AD7854/AD7854L provides flexible power management to
allow the user to achieve the best power performance for a given
throughput rate. The power management options are selected
by programming the power management bits, PMGT1 and
PMGT0, in the control register. Table VI summarizes the power-
down options that are available and how they can be selected by
programming the power management bits in the control register.
The AD7854/AD7854L can be fully or partially powered down.
When fully powered down, all the on-chip circuitry is powered
down and I
then all the on-chip circuitry except the reference is powered
down and I
Additional power savings may be made if the external clock is off.
The choice of full or partial power-down does not give any
significant improvement in the throughput rate which can be
achieved with a power-down between conversions. This is dis-
cussed in the next section—Power-Up Times. But a partial
power-down does allow the on-chip reference to be used exter-
nally even though the rest of the AD7854/AD7854L circuitry is
powered down. It also allows the AD7854/AD7854L to be pow-
ered up faster after a long power-down period when using the
on-chip reference (See Power-Up Times section—Using the
Internal (On-Chip) Reference).
As can be seen from Table VI, the AD7854/AD7854L can be
programmed for normal operation, a full power-down at the end
of a conversion, a partial power-down at the end of a conversion
and finally a full power-down whether converting or not. The
full and partial power-down at the end of a conversion can be
used to achieve a superior power performance at slower through-
put rates, in the order of 50 kSPS (see Power vs. Throughput Rate
section of this data sheet).
PMGT1 PMGT0
Bit
0
0
1
1
–78
–80
–82
–84
–86
–88
–90
Bit
0
1
0
1
0
DD
DD
Table VI. Power Management Options
is 10 µA typ. If a partial power-down is selected,
is 400 µA typ with the external clock running.
Figure 20. PSRR vs. Frequency
20
Comment
Normal Operation
Full Power-Down After a Conversion
Full Power-Down
Partial Power-Down After a Conversion
100mV pk-pk SINE WAVE ON AV
INPUT FREQUENCY – kHz
AV
40
DD
= DV
DD
= 3.3V/5.0V,
60
3.3V
80
DD
5.0V
100
–17–
POWER-UP TIMES
Using an External Reference
When the AD7854/AD7854L are powered up, the parts are
powered up from one of two conditions. First, when the power
supplies are initially powered up and, secondly, when the parts
are powered up from a software power-down (see last section).
When AV
enters a mode whereby the CONVST signal initiates a timeout
followed by a self-calibration. The total time taken for this time-
out and calibration is approximately 70 ms—see Calibration on
Power-Up in the calibration section of this data sheet. The power-
up calibration mode can be disabled if the user writes to the control
register before a CONVST signal is applied. If the timeout and
self-calibration are disabled, then the user must take into account
the time required by the AD7854/AD7854L to power up before
a self-calibration is carried out. This power-up time is the time
taken for the AD7854/AD7854L to power up when power is
first applied (300 µs typ) or the time it takes the external refer-
ence to settle to the 12-bit level—whichever is the longer.
The AD7854/AD7854L powers up from a full software power-
down in 5 µs typ. This limits the throughput which the part is
capable of to 100 kSPS for the AD7854 and 60 kSPS for the
AD7854L when powering down between conversions. Figure 21
shows how a full power-down between conversions is implemented
using the CONVST pin. The user first selects the power-down
between conversions option by setting the power management
bits, PMGT1 and PMGT0, to 0 and 1 respectively in the control
register (see last section). In this mode the AD7854/AD7854L
automatically enters a full power-down at the end of a conver-
sion, i.e., when BUSY goes low. The falling edge of the next
CONVST pulse causes the part to power up. Assuming the
external reference is left powered up, the AD7854/AD7854L
should be ready for normal operation 5 µs after this falling edge.
The rising edge of CONVST initiates a conversion so the
CONVST pulse should be at least 5 µs wide. The part auto-
matically powers down on completion of the conversion. Where
the software convert start is used, the part may be powered up in
software before a conversion is initiated.
Figure 21. Using the CONVST Pin to Power Up the AD7854
for a Conversion
CONVST
BUSY
DD
and DV
POWER-UP
TIME
5 s
DD
POWER-UP ON FALLING EDGE
are powered up, the AD7854/AD7854L
OPERATION
t
NORMAL
CONVERT
4.6 s
START CONVERSION ON RISING EDGE
AD7854/AD7854L
POWER-DOWN
FULL
POWER-UP
TIME